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Searched refs:mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfxhub_v1_0.c48 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v1_0_init_gart_pt_regs()
352 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); in gfxhub_v1_0_init()
H A Dmmhub_v1_0.c58 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v1_0_init_gart_pt_regs()
600 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); in mmhub_v1_0_init()
H A Damdgpu_amdkfd_gfx_v9.c1049 …WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(… in set_vm_context_page_table_base()
/dragonfly/sys/dev/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_0_offset.h1538 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 … macro
H A Dmmhub_9_1_offset.h1570 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 … macro
H A Dmmhub_9_3_0_offset.h1554 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h1416 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 … macro
H A Dgc_9_1_offset.h1460 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 … macro
H A Dgc_9_2_1_offset.h1398 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 … macro