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Searched refs:power_state (Results 1 – 25 of 37) sorted by relevance

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/dragonfly/sys/dev/drm/radeon/
H A Dradeon_atombios.c2049 rdev->pm.power_state[state_index].type = in radeon_atombios_parse_misc_flags_1_3()
2121 if (!rdev->pm.power_state) in radeon_atombios_parse_power_table_1_3()
2563 union pplib_power_state *power_state; in radeon_atombios_parse_power_table_4_5() local
2583 if (!rdev->pm.power_state) in radeon_atombios_parse_power_table_4_5()
2638 rdev->pm.power_state[0].type = in radeon_atombios_parse_power_table_4_5()
2651 union pplib_power_state *power_state; in radeon_atombios_parse_power_table_6() local
2684 if (!rdev->pm.power_state) in radeon_atombios_parse_power_table_6()
2699 if (power_state->v2.ucNumDPMLevels) { in radeon_atombios_parse_power_table_6()
2733 rdev->pm.power_state[0].type = in radeon_atombios_parse_power_table_6()
2774 if (rdev->pm.power_state) { in radeon_atombios_get_power_modes()
[all …]
H A Dradeon_combios.c2642 if (rdev->pm.power_state) { in radeon_combios_get_power_modes()
2644 rdev->pm.power_state[0].clock_info = in radeon_combios_get_power_modes()
2646 rdev->pm.power_state[1].clock_info = in radeon_combios_get_power_modes()
2648 if (!rdev->pm.power_state[0].clock_info || in radeon_combios_get_power_modes()
2649 !rdev->pm.power_state[1].clock_info) in radeon_combios_get_power_modes()
2732 rdev->pm.power_state[state_index].type = in radeon_combios_get_power_modes()
2737 rdev->pm.power_state[state_index].misc = misc; in radeon_combios_get_power_modes()
2798 rdev->pm.power_state[state_index].type = in radeon_combios_get_power_modes()
2803 …rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_in… in radeon_combios_get_power_modes()
2807 rdev->pm.power_state[0].clock_info[0].voltage; in radeon_combios_get_power_modes()
[all …]
H A Dradeon_pm.c61 if (rdev->pm.power_state[i].type == ps_type) { in radeon_pm_get_type_index()
323 struct radeon_power_state *power_state; in radeon_pm_print_states() local
328 power_state = &rdev->pm.power_state[i]; in radeon_pm_print_states()
339 clock_info = &(power_state->clock_info[j]); in radeon_pm_print_states()
1299 if (rdev->pm.power_state) { in radeon_pm_resume_old()
1678 if (rdev->pm.power_state) { in radeon_pm_fini_old()
1683 kfree(rdev->pm.power_state); in radeon_pm_fini_old()
1684 rdev->pm.power_state = NULL; in radeon_pm_fini_old()
1709 if (rdev->pm.power_state) { in radeon_pm_fini_dpm()
1714 kfree(rdev->pm.power_state); in radeon_pm_fini_dpm()
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H A Dtrinity_dpm.c1738 union pplib_power_state *power_state; in trinity_parse_power_table() local
1773 power_state = (union pplib_power_state *)power_state_offset; in trinity_parse_power_table()
1774 non_clock_array_index = power_state->v2.nonClockInfoIndex; in trinity_parse_power_table()
1777 if (!rdev->pm.power_state[i].clock_info) in trinity_parse_power_table()
1786 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; in trinity_parse_power_table()
1787 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in trinity_parse_power_table()
1804 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in trinity_parse_power_table()
H A Dsumo_dpm.c1459 union pplib_power_state *power_state; in sumo_parse_power_table() local
1494 power_state = (union pplib_power_state *)power_state_offset; in sumo_parse_power_table()
1495 non_clock_array_index = power_state->v2.nonClockInfoIndex; in sumo_parse_power_table()
1498 if (!rdev->pm.power_state[i].clock_info) in sumo_parse_power_table()
1507 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; in sumo_parse_power_table()
1508 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in sumo_parse_power_table()
1524 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in sumo_parse_power_table()
H A Drs780_dpm.c793 union pplib_power_state *power_state; in rs780_parse_power_table() local
813 power_state = (union pplib_power_state *) in rs780_parse_power_table()
820 (power_state->v1.ucNonClockStateIndex * in rs780_parse_power_table()
826 (power_state->v1.ucClockStateIndices[0] * in rs780_parse_power_table()
H A Dr600.c379 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
402 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
415 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
450 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
452 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || in r600_pm_get_dynpm_state()
453 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { in r600_pm_get_dynpm_state()
483 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
517 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
519 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
521 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
[all …]
H A Datombios_dp.c520 u8 power_state) in radeon_dp_set_rx_power_state() argument
533 DP_SET_POWER, power_state); in radeon_dp_set_rx_power_state()
H A Dkv_dpm.c2632 union pplib_power_state *power_state; in kv_parse_power_table() local
2667 power_state = (union pplib_power_state *)power_state_offset; in kv_parse_power_table()
2668 non_clock_array_index = power_state->v2.nonClockInfoIndex; in kv_parse_power_table()
2671 if (!rdev->pm.power_state[i].clock_info) in kv_parse_power_table()
2680 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; in kv_parse_power_table()
2681 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in kv_parse_power_table()
2698 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in kv_parse_power_table()
H A Dr100.c225 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r100_pm_get_dynpm_state()
241 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & in r100_pm_get_dynpm_state()
253 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r100_pm_get_dynpm_state()
281 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r100_pm_get_dynpm_state()
283 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r100_pm_get_dynpm_state()
285 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r100_pm_get_dynpm_state()
348 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; in r100_pm_misc()
429 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { in r100_pm_misc()
/dragonfly/sys/dev/netif/ath/ath/
H A Dif_ath_misc.h111 extern void _ath_power_setpower(struct ath_softc *sc, int power_state, const char *file, int line);
112 extern void _ath_power_set_selfgen(struct ath_softc *sc, int power_state, const char *file, int lin…
113 extern void _ath_power_set_power_state(struct ath_softc *sc, int power_state, const char *file, int…
H A Dif_ath.c318 sc->sc_target_powerstate = power_state; in _ath_power_setpower()
324 power_state, in _ath_power_setpower()
328 power_state != sc->sc_cur_powerstate) { in _ath_power_setpower()
329 sc->sc_cur_powerstate = power_state; in _ath_power_setpower()
330 ath_hal_setpower(sc->sc_ah, power_state); in _ath_power_setpower()
366 power_state, in _ath_power_set_selfgen()
369 sc->sc_target_selfgen_state = power_state; in _ath_power_set_selfgen()
401 power_state, in _ath_power_set_power_state()
406 if (power_state != sc->sc_cur_powerstate) { in _ath_power_set_power_state()
407 ath_hal_setpower(sc->sc_ah, power_state); in _ath_power_set_power_state()
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/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dvega12_processpptables.c394 uint32_t entry_index, struct pp_power_state *power_state,
406 power_state->classification.bios_index = entry_index;
426 result = call_back_func(hwmgr, (void *)state_entry, power_state,
433 if (!result && (power_state->classification.flags &
435 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
H A Dprocess_pptables_v1_0.h31 struct pp_power_state *power_state, int (*call_back_func)(struct pp_hwmgr *, void *,
H A Dvega10_processpptables.h60 struct pp_power_state *power_state, int (*call_back_func)(struct pp_hwmgr *, void *,
H A Dprocess_pptables_v1_0.c1289 uint32_t entry_index, struct pp_power_state *power_state, in get_powerplay_table_entry_v1_0() argument
1301 power_state->classification.bios_index = entry_index; in get_powerplay_table_entry_v1_0()
1319 result = call_back_func(hwmgr, (void *)state_entry, power_state, in get_powerplay_table_entry_v1_0()
1326 if (!result && (power_state->classification.flags & in get_powerplay_table_entry_v1_0()
1328 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware)); in get_powerplay_table_entry_v1_0()
H A Dvega10_processpptables.c1282 uint32_t entry_index, struct pp_power_state *power_state, in vega10_get_powerplay_table_entry() argument
1294 power_state->classification.bios_index = entry_index; in vega10_get_powerplay_table_entry()
1314 result = call_back_func(hwmgr, (void *)state_entry, power_state, in vega10_get_powerplay_table_entry()
1321 if (!result && (power_state->classification.flags & in vega10_get_powerplay_table_entry()
1323 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware)); in vega10_get_powerplay_table_entry()
H A Dsmu7_hwmgr.c3119 void *state, struct pp_power_state *power_state, in smu7_get_pp_table_entry_callback_func_v1() argument
3140 power_state->classification.ui_label = in smu7_get_pp_table_entry_callback_func_v1()
3150 power_state->validation.disallowOnDC = in smu7_get_pp_table_entry_callback_func_v1()
3154 power_state->pcie.lanes = 0; in smu7_get_pp_table_entry_callback_func_v1()
3157 power_state->display.limitRefreshrate = false; in smu7_get_pp_table_entry_callback_func_v1()
3158 power_state->display.enableVariBright = in smu7_get_pp_table_entry_callback_func_v1()
3163 power_state->uvd_clocks.VCLK = 0; in smu7_get_pp_table_entry_callback_func_v1()
3164 power_state->uvd_clocks.DCLK = 0; in smu7_get_pp_table_entry_callback_func_v1()
3165 power_state->temperatures.min = 0; in smu7_get_pp_table_entry_callback_func_v1()
3166 power_state->temperatures.max = 0; in smu7_get_pp_table_entry_callback_func_v1()
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H A Dvega10_hwmgr.c2971 void *state, struct pp_power_state *power_state, in vega10_get_pp_table_entry_callback_func() argument
2998 power_state->classification.ui_label = in vega10_get_pp_table_entry_callback_func()
3007 power_state->classification.to_be_deleted = false; in vega10_get_pp_table_entry_callback_func()
3009 power_state->validation.disallowOnDC = in vega10_get_pp_table_entry_callback_func()
3014 power_state->display.limitRefreshrate = false; in vega10_get_pp_table_entry_callback_func()
3015 power_state->display.enableVariBright = in vega10_get_pp_table_entry_callback_func()
3019 power_state->validation.supportedPowerLevels = 0; in vega10_get_pp_table_entry_callback_func()
3020 power_state->uvd_clocks.VCLK = 0; in vega10_get_pp_table_entry_callback_func()
3021 power_state->uvd_clocks.DCLK = 0; in vega10_get_pp_table_entry_callback_func()
3022 power_state->temperatures.min = 0; in vega10_get_pp_table_entry_callback_func()
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/dragonfly/sys/gnu/dev/misc/apple_gmux/
H A Dapple-gmux.c126 enum vga_switcheroo_state power_state; member
564 sc->power_state = state; in gmux_set_discrete_state()
602 .power_state = gmux_set_power_state,
609 .power_state = gmux_set_power_state,
831 sc->power_state = VGA_SWITCHEROO_ON; in apple_gmux_attach()
/dragonfly/sys/dev/video/vga/
H A Dvga_switcheroo.c676 if (vgasr_priv->handler->power_state) in vga_switchon()
677 vgasr_priv->handler->power_state(client->id, VGA_SWITCHEROO_ON); in vga_switchon()
691 if (vgasr_priv->handler->power_state) in vga_switchoff()
692 vgasr_priv->handler->power_state(client->id, VGA_SWITCHEROO_OFF); in vga_switchoff()
1325 if (!vgasr_priv->handler->power_state)
1335 vgasr_priv->handler->power_state(client->id, state);
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Datombios_dp.h38 u8 power_state);
H A Datombios_dp.c460 u8 power_state) in amdgpu_atombios_dp_set_rx_power_state() argument
473 DP_SET_POWER, power_state); in amdgpu_atombios_dp_set_rx_power_state()
/dragonfly/sys/dev/drm/include/linux/
H A Dvga_switcheroo.h120 int (*power_state)(enum vga_switcheroo_client_id id, member
/dragonfly/sys/dev/drm/amd/display/dc/
H A Ddc.h751 enum dc_acpi_cm_power_state power_state);

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