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Searched refs:radeon_ring_write (Results 1 – 22 of 22) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dcik_sdma.c146 radeon_ring_write(ring, next_rptr); in cik_sdma_ring_ib_execute()
155 radeon_ring_write(ring, ib->length_dw); in cik_sdma_ring_ib_execute()
208 radeon_ring_write(ring, fence->seq); in cik_sdma_fence_ring_emit()
671 radeon_ring_write(ring, 0xDEADBEEF); in cik_sdma_ring_test()
966 radeon_ring_write(ring, 0); in cik_dma_vm_flush()
970 radeon_ring_write(ring, 0); in cik_dma_vm_flush()
974 radeon_ring_write(ring, 1); in cik_dma_vm_flush()
978 radeon_ring_write(ring, 0); in cik_dma_vm_flush()
982 radeon_ring_write(ring, VMID(0)); in cik_dma_vm_flush()
990 radeon_ring_write(ring, 1 << vm_id); in cik_dma_vm_flush()
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H A Duvd_v2_2.c45 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); in uvd_v2_2_fence_emit()
46 radeon_ring_write(ring, fence->seq); in uvd_v2_2_fence_emit()
48 radeon_ring_write(ring, lower_32_bits(addr)); in uvd_v2_2_fence_emit()
50 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); in uvd_v2_2_fence_emit()
52 radeon_ring_write(ring, 0); in uvd_v2_2_fence_emit()
55 radeon_ring_write(ring, 0); in uvd_v2_2_fence_emit()
57 radeon_ring_write(ring, 0); in uvd_v2_2_fence_emit()
59 radeon_ring_write(ring, 2); in uvd_v2_2_fence_emit()
80 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF); in uvd_v2_2_semaphore_emit()
85 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); in uvd_v2_2_semaphore_emit()
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H A Devergreen_dma.c45 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0)); in evergreen_dma_fence_ring_emit()
46 radeon_ring_write(ring, addr & 0xfffffffc); in evergreen_dma_fence_ring_emit()
47 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in evergreen_dma_fence_ring_emit()
48 radeon_ring_write(ring, fence->seq); in evergreen_dma_fence_ring_emit()
50 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0)); in evergreen_dma_fence_ring_emit()
54 radeon_ring_write(ring, 1); in evergreen_dma_fence_ring_emit()
78 radeon_ring_write(ring, next_rptr); in evergreen_dma_ring_ib_execute()
85 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0)); in evergreen_dma_ring_ib_execute()
87 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in evergreen_dma_ring_ib_execute()
139 radeon_ring_write(ring, dst_offset & 0xfffffffc); in evergreen_copy_dma()
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H A Duvd_v1_0.c92 radeon_ring_write(ring, 0); in uvd_v1_0_fence_emit()
95 radeon_ring_write(ring, 0); in uvd_v1_0_fence_emit()
97 radeon_ring_write(ring, 0); in uvd_v1_0_fence_emit()
99 radeon_ring_write(ring, 2); in uvd_v1_0_fence_emit()
187 radeon_ring_write(ring, tmp); in uvd_v1_0_init()
188 radeon_ring_write(ring, 0xFFFFF); in uvd_v1_0_init()
191 radeon_ring_write(ring, tmp); in uvd_v1_0_init()
192 radeon_ring_write(ring, 0xFFFFF); in uvd_v1_0_init()
195 radeon_ring_write(ring, tmp); in uvd_v1_0_init()
200 radeon_ring_write(ring, 0x8); in uvd_v1_0_init()
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H A Dsi_dma.c197 radeon_ring_write(ring, pd_addr >> 12); in si_dma_vm_flush()
202 radeon_ring_write(ring, 1); in si_dma_vm_flush()
207 radeon_ring_write(ring, 1 << vm_id); in si_dma_vm_flush()
211 radeon_ring_write(ring, VM_INVALIDATE_REQUEST); in si_dma_vm_flush()
212 radeon_ring_write(ring, 0xff << 16); /* retry */ in si_dma_vm_flush()
213 radeon_ring_write(ring, 1 << vm_id); /* mask */ in si_dma_vm_flush()
214 radeon_ring_write(ring, 0); /* value */ in si_dma_vm_flush()
264 radeon_ring_write(ring, lower_32_bits(dst_offset)); in si_copy_dma()
265 radeon_ring_write(ring, lower_32_bits(src_offset)); in si_copy_dma()
266 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in si_copy_dma()
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H A Dr600_dma.c253 radeon_ring_write(ring, lower_32_bits(gpu_addr)); in r600_dma_ring_test()
255 radeon_ring_write(ring, 0xDEADBEEF); in r600_dma_ring_test()
293 radeon_ring_write(ring, addr & 0xfffffffc); in r600_dma_fence_ring_emit()
294 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in r600_dma_fence_ring_emit()
295 radeon_ring_write(ring, lower_32_bits(fence->seq)); in r600_dma_fence_ring_emit()
320 radeon_ring_write(ring, addr & 0xfffffffc); in r600_dma_semaphore_ring_emit()
321 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); in r600_dma_semaphore_ring_emit()
415 radeon_ring_write(ring, next_rptr); in r600_dma_ring_ib_execute()
424 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in r600_dma_ring_ib_execute()
475 radeon_ring_write(ring, dst_offset & 0xfffffffc); in r600_copy_dma()
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H A Dni_dma.c131 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); in cayman_dma_ring_ib_execute()
132 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in cayman_dma_ring_ib_execute()
134 radeon_ring_write(ring, next_rptr); in cayman_dma_ring_ib_execute()
141 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); in cayman_dma_ring_ib_execute()
143 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in cayman_dma_ring_ib_execute()
452 radeon_ring_write(ring, pd_addr >> 12); in cayman_dma_vm_flush()
457 radeon_ring_write(ring, 1); in cayman_dma_vm_flush()
462 radeon_ring_write(ring, 1 << vm_id); in cayman_dma_vm_flush()
465 radeon_ring_write(ring, DMA_SRBM_READ_PACKET); in cayman_dma_vm_flush()
467 radeon_ring_write(ring, 0); /* mask */ in cayman_dma_vm_flush()
[all …]
H A Dr300.c213 radeon_ring_write(ring, 0); in r300_fence_ring_emit()
215 radeon_ring_write(ring, 0); in r300_fence_ring_emit()
266 radeon_ring_write(ring, in r300_ring_start()
274 radeon_ring_write(ring, in r300_ring_start()
280 radeon_ring_write(ring, 0); in r300_ring_start()
282 radeon_ring_write(ring, 0); in r300_ring_start()
288 radeon_ring_write(ring, in r300_ring_start()
298 radeon_ring_write(ring, in r300_ring_start()
308 radeon_ring_write(ring, in r300_ring_start()
319 radeon_ring_write(ring, in r300_ring_start()
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H A Dni.c1423 radeon_ring_write(ring, 0); in cayman_fence_ring_emit()
1431 radeon_ring_write(ring, 0); in cayman_fence_ring_emit()
1443 radeon_ring_write(ring, 1); in cayman_ring_ib_execute()
1454 radeon_ring_write(ring, in cayman_ring_ib_execute()
1466 radeon_ring_write(ring, 0); in cayman_ring_ib_execute()
1570 radeon_ring_write(ring, 0x1); in cayman_cp_start()
1571 radeon_ring_write(ring, 0x0); in cayman_cp_start()
1574 radeon_ring_write(ring, 0); in cayman_cp_start()
1575 radeon_ring_write(ring, 0); in cayman_cp_start()
1598 radeon_ring_write(ring, 0); in cayman_cp_start()
[all …]
H A Duvd_v3_1.c47 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); in uvd_v3_1_semaphore_emit()
48 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF); in uvd_v3_1_semaphore_emit()
50 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); in uvd_v3_1_semaphore_emit()
51 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF); in uvd_v3_1_semaphore_emit()
53 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); in uvd_v3_1_semaphore_emit()
54 radeon_ring_write(ring, 0x80 | (emit_wait ? 1 : 0)); in uvd_v3_1_semaphore_emit()
H A Drv515.c70 radeon_ring_write(ring, in rv515_ring_start()
80 radeon_ring_write(ring, 0); in rv515_ring_start()
82 radeon_ring_write(ring, 0); in rv515_ring_start()
86 radeon_ring_write(ring, 0); in rv515_ring_start()
90 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); in rv515_ring_start()
94 radeon_ring_write(ring, 0); in rv515_ring_start()
98 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); in rv515_ring_start()
100 radeon_ring_write(ring, in rv515_ring_start()
110 radeon_ring_write(ring, in rv515_ring_start()
124 radeon_ring_write(ring, PACKET0(0x20C8, 0)); in rv515_ring_start()
[all …]
H A Drv770_dma.c74 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); in rv770_copy_dma()
75 radeon_ring_write(ring, dst_offset & 0xfffffffc); in rv770_copy_dma()
76 radeon_ring_write(ring, src_offset & 0xfffffffc); in rv770_copy_dma()
77 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in rv770_copy_dma()
78 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in rv770_copy_dma()
H A Dradeon_vce.c702 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_SEMAPHORE)); in radeon_vce_semaphore_emit()
707 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END)); in radeon_vce_semaphore_emit()
722 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_IB)); in radeon_vce_ib_execute()
723 radeon_ring_write(ring, cpu_to_le32(ib->gpu_addr)); in radeon_vce_ib_execute()
725 radeon_ring_write(ring, cpu_to_le32(ib->length_dw)); in radeon_vce_ib_execute()
741 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_FENCE)); in radeon_vce_fence_emit()
742 radeon_ring_write(ring, cpu_to_le32(addr)); in radeon_vce_fence_emit()
744 radeon_ring_write(ring, cpu_to_le32(fence->seq)); in radeon_vce_fence_emit()
745 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_TRAP)); in radeon_vce_fence_emit()
746 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END)); in radeon_vce_fence_emit()
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H A Dr600.c2707 radeon_ring_write(ring, 0x1); in r600_cp_start()
2709 radeon_ring_write(ring, 0x0); in r600_cp_start()
2712 radeon_ring_write(ring, 0x3); in r600_cp_start()
2716 radeon_ring_write(ring, 0); in r600_cp_start()
2717 radeon_ring_write(ring, 0); in r600_cp_start()
2892 radeon_ring_write(ring, 0); in r600_fence_ring_emit()
2900 radeon_ring_write(ring, 0); in r600_fence_ring_emit()
2906 radeon_ring_write(ring, 0); in r600_fence_ring_emit()
2954 radeon_ring_write(ring, 0x0); in r600_semaphore_ring_emit()
3397 radeon_ring_write(ring, 0); in r600_ring_ib_execute()
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H A Dcik.c3598 radeon_ring_write(ring, 0); in cik_fence_gfx_ring_emit()
3609 radeon_ring_write(ring, 0); in cik_fence_gfx_ring_emit()
3637 radeon_ring_write(ring, 0); in cik_fence_compute_ring_emit()
4051 radeon_ring_write(ring, 0); in cik_cp_gfx_start()
5722 radeon_ring_write(ring, in cik_vm_flush()
5725 radeon_ring_write(ring, in cik_vm_flush()
5728 radeon_ring_write(ring, 0); in cik_vm_flush()
5736 radeon_ring_write(ring, 0); in cik_vm_flush()
5743 radeon_ring_write(ring, 0); in cik_vm_flush()
5754 radeon_ring_write(ring, 0); in cik_vm_flush()
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H A Dsi.c3369 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3376 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3384 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3423 radeon_ring_write(ring, in si_ring_ib_execute()
3563 radeon_ring_write(ring, 0); in si_cp_start()
3564 radeon_ring_write(ring, 0); in si_cp_start()
3593 radeon_ring_write(ring, 0); in si_cp_start()
5071 radeon_ring_write(ring, in si_vm_flush()
5074 radeon_ring_write(ring, in si_vm_flush()
5077 radeon_ring_write(ring, 0); in si_vm_flush()
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H A Dr200.c105 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r200_copy_dma()
106 radeon_ring_write(ring, (1 << 16)); in r200_copy_dma()
113 radeon_ring_write(ring, PACKET0(0x720, 2)); in r200_copy_dma()
114 radeon_ring_write(ring, src_offset); in r200_copy_dma()
115 radeon_ring_write(ring, dst_offset); in r200_copy_dma()
116 radeon_ring_write(ring, cur_size | (1 << 31) | (1 << 30)); in r200_copy_dma()
120 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r200_copy_dma()
121 radeon_ring_write(ring, RADEON_WAIT_DMA_GUI_IDLE); in r200_copy_dma()
H A Dr100.c869 radeon_ring_write(ring, fence->seq); in r100_fence_ring_emit()
924 radeon_ring_write(ring, in r100_copy_blit()
939 radeon_ring_write(ring, 0); in r100_copy_blit()
941 radeon_ring_write(ring, num_gpu_pages); in r100_copy_blit()
942 radeon_ring_write(ring, num_gpu_pages); in r100_copy_blit()
948 radeon_ring_write(ring, in r100_copy_blit()
985 radeon_ring_write(ring, in r100_ring_start()
3681 radeon_ring_write(ring, 0xDEADBEEF); in r100_ring_test()
3708 radeon_ring_write(ring, next_rptr); in r100_ring_ib_execute()
3712 radeon_ring_write(ring, ib->gpu_addr); in r100_ring_ib_execute()
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H A Dr420.c218 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); in r420_cp_errata_init()
219 radeon_ring_write(ring, rdev->config.r300.resync_scratch); in r420_cp_errata_init()
220 radeon_ring_write(ring, 0xDEADBEEF); in r420_cp_errata_init()
234 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); in r420_cp_errata_fini()
235 radeon_ring_write(ring, R300_RB3D_DC_FINISH); in r420_cp_errata_fini()
H A Devergreen.c2919 radeon_ring_write(ring, 1); in evergreen_ring_ib_execute()
2926 radeon_ring_write(ring, next_rptr); in evergreen_ring_ib_execute()
2932 radeon_ring_write(ring, next_rptr); in evergreen_ring_ib_execute()
2933 radeon_ring_write(ring, 0); in evergreen_ring_ib_execute()
2937 radeon_ring_write(ring, in evergreen_ring_ib_execute()
2991 radeon_ring_write(ring, 0x1); in evergreen_cp_start()
2992 radeon_ring_write(ring, 0x0); in evergreen_cp_start()
2995 radeon_ring_write(ring, 0); in evergreen_cp_start()
2996 radeon_ring_write(ring, 0); in evergreen_cp_start()
3020 radeon_ring_write(ring, 0); in evergreen_cp_start()
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H A Dradeon_ring.c174 radeon_ring_write(ring, ring->nop); in radeon_ring_commit()
355 radeon_ring_write(ring, data[i]); in radeon_ring_restore()
H A Dradeon.h2709 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) in radeon_ring_write() function