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Searched refs:reg_class (Results 1 – 25 of 87) sorted by relevance

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/dragonfly/contrib/wpa_supplicant/src/p2p/
H A Dp2p_utils.c85 res->reg_class = a->reg_class; in p2p_reg_class_intersect()
123 if (a_reg->reg_class != b_reg->reg_class) in p2p_channels_intersect()
127 &res->reg_class[res->reg_classes]); in p2p_channels_intersect()
171 if (cl->reg_class != b_cl->reg_class) in p2p_channels_union_inplace()
182 if (cl->reg_class == b_cl->reg_class) in p2p_channels_union_inplace()
238 os_memmove(&chan->reg_class[o], &chan->reg_class[o + 1], in p2p_channels_remove_freqs()
260 if (reg->reg_class != reg_class) in p2p_channels_includes()
278 if (p2p_channel_to_freq(reg->reg_class, in p2p_channels_includes_freq()
353 c = &chan->reg_class[i]; in p2p_channels_dump()
401 *op_class = c->reg_class; in p2p_channel_select()
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H A Dp2p_invitation.c112 u8 reg_class, u8 channel, in p2p_build_invitation_resp() argument
153 if (reg_class && channel) in p2p_build_invitation_resp()
155 reg_class, channel); in p2p_build_invitation_resp()
185 u8 reg_class = 0, channel = 0; in p2p_process_invitation_req() local
278 if (p2p_freq_to_channel(op_freq, &reg_class, &channel) < 0) { in p2p_process_invitation_req()
285 if (!p2p_channels_includes(&intersection, reg_class, channel)) in p2p_process_invitation_req()
367 reg_class = p2p->op_reg_class; in p2p_process_invitation_req()
379 bssid, reg_class, channel, channels); in p2p_process_invitation_req()
387 freq = p2p_channel_to_freq(p2p->cfg->reg_class, in p2p_process_invitation_req()
H A Dp2p_build.c86 u8 reg_class, u8 channel) in p2p_buf_add_listen_channel() argument
92 wpabuf_put_u8(buf, reg_class); /* Regulatory Class */ in p2p_buf_add_listen_channel()
95 "Channel %u", reg_class, channel); in p2p_buf_add_listen_channel()
100 u8 reg_class, u8 channel) in p2p_buf_add_operating_channel() argument
106 wpabuf_put_u8(buf, reg_class); /* Regulatory Class */ in p2p_buf_add_operating_channel()
109 "Channel %u", reg_class, channel); in p2p_buf_add_operating_channel()
163 struct p2p_reg_class *c = &chan->reg_class[i]; in p2p_buf_add_channel_list()
164 wpabuf_put_u8(buf, c->reg_class); in p2p_buf_add_channel_list()
/dragonfly/contrib/gcc-8.0/gcc/
H A Dira.h40 enum reg_class x_ira_hard_regno_allocno_class[FIRST_PSEUDO_REGISTER];
48 enum reg_class x_ira_allocno_classes[N_REG_CLASSES];
53 enum reg_class x_ira_allocno_class_translate[N_REG_CLASSES];
61 enum reg_class x_ira_pressure_classes[N_REG_CLASSES];
67 enum reg_class x_ira_pressure_class_translate[N_REG_CLASSES];
71 enum reg_class x_ira_stack_reg_pressure_class;
101 enum reg_class x_ira_reg_class_subset[N_REG_CLASSES][N_REG_CLASSES];
H A Dira-costs.c92 static enum reg_class *pref;
95 static enum reg_class *pref_buffer;
338 enum reg_class cl; in setup_regno_cost_classes_by_aclass()
522 enum reg_class rclass; in record_reg_classes()
765 enum reg_class cl; in record_reg_classes()
1100 enum reg_class rclass; in record_address_regs()
1231 enum reg_class i; in record_address_regs()
1234 enum reg_class *cost_classes; in record_address_regs()
2021 enum reg_class rclass; in process_bb_node_for_hard_reg_moves()
2218 pref_buffer = (enum reg_class *) ira_allocate (sizeof (enum reg_class) in init_costs()
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H A Dira-lives.c183 enum reg_class cl; in inc_register_pressure()
210 enum reg_class cl; in dec_register_pressure()
266 enum reg_class pclass; in mark_pseudo_regno_live()
305 enum reg_class pclass; in mark_pseudo_regno_subword_live()
399 enum reg_class cl; in mark_pseudo_regno_dead()
434 enum reg_class cl; in mark_pseudo_regno_subword_dead()
754 static enum reg_class
816 static enum reg_class
833 enum reg_class cl; in ira_implicitly_set_insn_hard_regs()
882 enum reg_class cl; in process_single_reg_class_operands()
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H A Dregrename.h71 ENUM_BITFIELD(reg_class) cl : 16;
101 extern int find_rename_reg (du_head_p, enum reg_class, HARD_REG_SET *, int,
104 extern reg_class regrename_find_superclass (du_head_p, int *,
H A Dreload.h84 enum reg_class rclass;
338 extern enum reg_class scratch_reload_class (enum insn_code);
399 extern rtx find_equiv_reg (rtx, rtx_insn *, enum reg_class, int, short *,
409 extern int push_reload (rtx, rtx, rtx *, rtx *, enum reg_class,
H A Dreginfo.c307 reg_class_subunion[i][j] = (enum reg_class) k; in init_reg_sets_1()
329 reg_class_superunion[i][j] = (enum reg_class) k; in init_reg_sets_1()
353 enum reg_class *p; in init_reg_sets_1()
358 *p = (enum reg_class) i; in init_reg_sets_1()
858 enum reg_class
865 return (enum reg_class) reg_pref[regno].prefclass; in reg_preferred_class()
868 enum reg_class
875 return (enum reg_class) reg_pref[regno].altclass; in reg_alternate_class()
879 enum reg_class
1021 enum reg_class prefclass, enum reg_class altclass, in setup_reg_classes()
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H A Dlra.h30 static inline enum reg_class
37 extern rtx lra_create_new_reg (machine_mode, rtx, enum reg_class,
H A Dira.c551 enum reg_class *p; in setup_reg_subclasses()
750 enum reg_class cl; in setup_stack_reg_pressure_class()
1056 = (enum reg_class) cl; in setup_allocno_and_important_classes()
1165 enum reg_class cl1 = *(const enum reg_class *) v1p; in comp_reg_classes_func()
1166 enum reg_class cl2 = *(const enum reg_class *) v2p; in comp_reg_classes_func()
1257 enum reg_class *p; in setup_reg_class_relations()
1452 enum reg_class cl; in setup_hard_regno_aclass()
1628 enum reg_class *p1, *p2; in ira_init_register_move_cost()
2200 enum reg_class pref; in ira_bad_reload_regno_1()
2381 enum reg_class pclass; in setup_reg_renumber()
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H A Dira-int.h289 ENUM_BITFIELD (reg_class) aclass : 16;
863 enum reg_class x_ira_important_classes[N_REG_CLASSES];
878 enum reg_class x_ira_reg_class_intersect[N_REG_CLASSES][N_REG_CLASSES];
884 enum reg_class x_ira_reg_class_super_classes[N_REG_CLASSES][N_REG_CLASSES];
893 enum reg_class x_ira_reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
894 enum reg_class x_ira_reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
899 enum reg_class x_alloc_reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
995 extern void ira_set_allocno_class (ira_allocno_t, enum reg_class);
1455 ira_allocate_and_copy_costs (int **vec, enum reg_class aclass, int *src) in ira_allocate_and_copy_costs()
1469 ira_allocate_and_accumulate_costs (int **vec, enum reg_class aclass, int *src) in ira_allocate_and_accumulate_costs()
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H A Dregrename.c228 rtx_insn *insn, enum reg_class cl) in create_new_chain()
358 find_rename_reg (du_head_p this_head, enum reg_class super_class, in find_rename_reg()
362 enum reg_class preferred_class; in find_rename_reg()
378 = (enum reg_class) targetm.preferred_rename_class (super_class); in find_rename_reg()
433 reg_class
438 reg_class super_class = NO_REGS; in regrename_find_superclass()
1254 static reg_class
1267 scan_rtx_address (rtx_insn *insn, rtx *loc, enum reg_class cl, in scan_rtx_address()
1396 reg_class bclass = base_reg_class_for_rename (insn, GET_MODE (x), in scan_rtx_address()
1589 enum reg_class cl = alternative_class (op_alt, opn); in record_out_operands()
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H A Dlra-constraints.c174 enum reg_class rclass; in get_try_hard_regno()
217 static enum reg_class
243 in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class) in in_class_p()
1090 static enum reg_class
1370 enum reg_class cl) in process_addr_reg()
1943 enum reg_class cl; in process_alt_operands()
3040 enum reg_class cl; in base_to_reg()
3073 enum reg_class cl; in base_plus_disp_to_reg()
5147 enum reg_class cl; in check_secondary_memory_needed_p()
5418 static enum reg_class
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H A Dlra-assigns.c109 static enum reg_class *regno_allocno_class_array;
202 enum reg_class cl1 = regno_allocno_class_array[r1]; in reload_pseudo_compare_func()
203 enum reg_class cl2 = regno_allocno_class_array[r2]; in reload_pseudo_compare_func()
490 enum reg_class rclass; in find_hard_regno_for_1()
702 enum reg_class pref_class = reg_preferred_class (regno); in find_hard_regno_for()
831 setup_try_hard_regno_pseudos (int p, enum reg_class rclass) in setup_try_hard_regno_pseudos()
934 enum reg_class rclass; in spill_for()
1323 enum reg_class rclass; in find_all_spills_for()
1541 enum reg_class spill_class; in assign_by_spills()
1547 = ((enum reg_class) in assign_by_spills()
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H A Dtarghooks.c1100 enum reg_class rclass = NO_REGS; in default_secondary_reload()
1101 enum reg_class reload_class = (enum reg_class) reload_class_i; in default_secondary_reload()
1130 enum reg_class insn_class, scratch_class; in default_secondary_reload()
1659 return (4 + memory_move_secondary_cost (mode, (enum reg_class) rclass, in)); in default_memory_move_cost()
1661 return MEMORY_MOVE_COST (MACRO_MODE (mode), (enum reg_class) rclass, in); in default_memory_move_cost()
1677 (enum reg_class) from, (enum reg_class) to); in default_register_move_cost()
1829 return (reg_class_t) PREFERRED_RELOAD_CLASS (x, (enum reg_class) rclass); in default_preferred_reload_class()
1866 return (unsigned char) CLASS_MAX_NREGS ((enum reg_class) rclass, in default_class_max_nregs()
/dragonfly/contrib/gcc-4.7/gcc/
H A Dira.h35 enum reg_class x_ira_hard_regno_allocno_class[FIRST_PSEUDO_REGISTER];
43 enum reg_class x_ira_allocno_classes[N_REG_CLASSES];
48 enum reg_class x_ira_allocno_class_translate[N_REG_CLASSES];
56 enum reg_class x_ira_pressure_classes[N_REG_CLASSES];
62 enum reg_class x_ira_pressure_class_translate[N_REG_CLASSES];
66 enum reg_class x_ira_stack_reg_pressure_class;
H A Dira-costs.c96 static enum reg_class *pref;
99 static enum reg_class *pref_buffer;
197 enum reg_class cl; in setup_cost_classes()
231 enum reg_class cl; in setup_regno_cost_classes_by_aclass()
295 enum reg_class cl; in setup_regno_cost_classes_by_mode()
429 enum reg_class rclass; in record_reg_classes()
1029 enum reg_class rclass; in record_address_regs()
1165 enum reg_class i; in record_address_regs()
1168 enum reg_class *cost_classes; in record_address_regs()
2026 pref_buffer = (enum reg_class *) ira_allocate (sizeof (enum reg_class) in init_costs()
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H A Dreginfo.c219 (enum reg_class) j); in init_move_cost()
244 enum reg_class *p1, *p2; in init_move_cost()
269 if (reg_class_subset_p ((enum reg_class) i, (enum reg_class) j)) in init_move_cost()
274 if (reg_class_subset_p ((enum reg_class) j, (enum reg_class) i)) in init_move_cost()
444 enum reg_class *p; in init_reg_sets_1()
449 *p = (enum reg_class) i; in init_reg_sets_1()
958 enum reg_class
967 enum reg_class
977 enum reg_class
1083 enum reg_class prefclass, enum reg_class altclass, in setup_reg_classes()
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H A Dira-lives.c185 enum reg_class cl; in inc_register_pressure()
212 enum reg_class cl; in dec_register_pressure()
250 enum reg_class pclass; in mark_pseudo_regno_live()
289 enum reg_class pclass; in mark_pseudo_regno_subword_live()
383 enum reg_class cl; in mark_pseudo_regno_dead()
418 enum reg_class cl; in mark_pseudo_regno_subword_dead()
726 static enum reg_class
864 static enum reg_class
881 enum reg_class cl; in ira_implicitly_set_insn_hard_regs()
946 enum reg_class cl; in process_single_reg_class_operands()
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H A Dira.c554 enum reg_class *p; in setup_reg_subclasses()
563 *p = (enum reg_class) i; in setup_reg_subclasses()
753 enum reg_class cl; in setup_stack_reg_pressure_class()
1128 enum reg_class cl1 = *(const enum reg_class *) v1p; in comp_reg_classes_func()
1129 enum reg_class cl2 = *(const enum reg_class *) v2p; in comp_reg_classes_func()
1130 enum reg_class tcl1, tcl2; in comp_reg_classes_func()
1219 enum reg_class *p; in setup_reg_class_relations()
1379 enum reg_class cl; in setup_hard_regno_aclass()
1690 enum reg_class pref; in ira_bad_reload_regno_1()
1949 enum reg_class pclass; in setup_reg_renumber()
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H A Dreload.h84 enum reg_class rclass;
339 extern enum reg_class scratch_reload_class (enum insn_code);
400 extern rtx find_equiv_reg (rtx, rtx, enum reg_class, int, short *,
410 extern int push_reload (rtx, rtx, rtx *, rtx *, enum reg_class,
H A Dira-int.h292 ENUM_BITFIELD (reg_class) aclass : 16;
829 enum reg_class x_ira_important_classes[N_REG_CLASSES];
841 enum reg_class x_ira_reg_class_intersect[N_REG_CLASSES][N_REG_CLASSES];
852 enum reg_class x_ira_reg_class_super_classes[N_REG_CLASSES][N_REG_CLASSES];
861 enum reg_class x_ira_reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
862 enum reg_class x_ira_reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
867 enum reg_class x_alloc_reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
971 extern void ira_set_allocno_class (ira_allocno_t, enum reg_class);
1372 ira_allocate_and_copy_costs (int **vec, enum reg_class aclass, int *src) in ira_allocate_and_copy_costs()
1386 ira_allocate_and_accumulate_costs (int **vec, enum reg_class aclass, int *src) in ira_allocate_and_accumulate_costs()
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H A Dtarghooks.c843 enum reg_class rclass = NO_REGS; in default_secondary_reload()
844 enum reg_class reload_class = (enum reg_class) reload_class_i; in default_secondary_reload()
872 enum reg_class insn_class, scratch_class; in default_secondary_reload()
1239 return (4 + memory_move_secondary_cost (mode, (enum reg_class) rclass, in)); in default_memory_move_cost()
1241 return MEMORY_MOVE_COST (mode, (enum reg_class) rclass, in); in default_memory_move_cost()
1256 return REGISTER_MOVE_COST (mode, (enum reg_class) from, (enum reg_class) to); in default_register_move_cost()
1277 return (reg_class_t) PREFERRED_RELOAD_CLASS (x, (enum reg_class) rclass); in default_preferred_reload_class()
1314 return (unsigned char) CLASS_MAX_NREGS ((enum reg_class) rclass, mode); in default_class_max_nregs()
H A Dregrename.h66 ENUM_BITFIELD(reg_class) cl : 16;
97 extern int find_best_rename_reg (du_head_p, enum reg_class, HARD_REG_SET *,

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