Searched refs:sclk_setting (Results 1 – 3 of 3) sorted by relevance
731 sclk_setting->SclkFrequency = clock; in vegam_calculate_sclk_params()739 sclk_setting->Sclk_slew_rate = 0x400; in vegam_calculate_sclk_params()741 sclk_setting->Pcc_down_slew_rate = 0xffff; in vegam_calculate_sclk_params()754 sclk_setting->PllRange = i; in vegam_calculate_sclk_params()759 sclk_setting->Fcw_int = (uint16_t) in vegam_calculate_sclk_params()765 sclk_setting->Fcw_frac = temp & 0xffff; in vegam_calculate_sclk_params()769 sclk_setting->Pcc_fcw_int = (uint16_t) in vegam_calculate_sclk_params()774 sclk_setting->SSc_En = 0; in vegam_calculate_sclk_params()776 sclk_setting->SSc_En = 1; in vegam_calculate_sclk_params()778 sclk_setting->Fcw1_int = (uint16_t) in vegam_calculate_sclk_params()[all …]
841 uint32_t clock, SMU_SclkSetting *sclk_setting) in polaris10_calculate_sclk_params() argument852 sclk_setting->SclkFrequency = clock; in polaris10_calculate_sclk_params()860 sclk_setting->Sclk_slew_rate = 0x400; in polaris10_calculate_sclk_params()862 sclk_setting->Pcc_down_slew_rate = 0xffff; in polaris10_calculate_sclk_params()863 sclk_setting->SSc_En = dividers.ucSscEnable; in polaris10_calculate_sclk_params()875 sclk_setting->PllRange = i; in polaris10_calculate_sclk_params()880 …sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].post… in polaris10_calculate_sclk_params()884 sclk_setting->Fcw_frac = temp & 0xffff; in polaris10_calculate_sclk_params()891 sclk_setting->SSc_En = 0; in polaris10_calculate_sclk_params()893 sclk_setting->SSc_En = 1; in polaris10_calculate_sclk_params()[all …]
2120 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting; member