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Searched refs:smc_addr (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
H A Dsmu7_smumgr.c38 static int smu7_set_smc_sram_address(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t limit) in smu7_set_smc_sram_address() argument
40 PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL); in smu7_set_smc_sram_address()
41 …PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINV… in smu7_set_smc_sram_address()
43 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, smc_addr); in smu7_set_smc_sram_address()
280 int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t *value, uint32_t l… in smu7_read_smc_sram_dword() argument
284 result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit); in smu7_read_smc_sram_dword()
291 int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t value, uint32_t l… in smu7_write_smc_sram_dword() argument
295 result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit); in smu7_write_smc_sram_dword()
H A Dsmu7_smumgr.h71 int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
73 int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
H A Dci_smumgr.c94 uint32_t smc_addr, uint32_t limit) in ci_set_smc_sram_address() argument
96 if ((0 != (3 & smc_addr)) in ci_set_smc_sram_address()
97 || ((smc_addr + 3) >= limit)) { in ci_set_smc_sram_address()
102 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, smc_addr); in ci_set_smc_sram_address()
194 static int ci_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, in ci_read_smc_sram_dword() argument
199 result = ci_set_smc_sram_address(hwmgr, smc_addr, limit); in ci_read_smc_sram_dword()