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Searched refs:spll (Results 1 – 25 of 28) sorted by relevance

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/dragonfly/sys/dev/drm/radeon/
H A Dradeon_clocks.c38 struct radeon_pll *spll = &rdev->clock.spll; in radeon_legacy_get_engine_clock() local
107 struct radeon_pll *spll = &rdev->clock.spll; in radeon_read_clocks_OF() local
182 struct radeon_pll *spll = &rdev->clock.spll; in radeon_get_clock_info() local
211 spll->reference_div = in radeon_get_clock_info()
263 spll->reference_div = in radeon_get_clock_info()
319 spll->min_post_div = 1; in radeon_get_clock_info()
320 spll->max_post_div = 1; in radeon_get_clock_info()
321 spll->min_ref_div = 2; in radeon_get_clock_info()
322 spll->max_ref_div = 0xff; in radeon_get_clock_info()
325 spll->best_vco = 0; in radeon_get_clock_info()
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H A Dradeon_combios.c731 struct radeon_pll *spll = &rdev->clock.spll; in radeon_combios_get_clock_info() local
758 spll->reference_freq = RBIOS16(pll_info + 0x1a); in radeon_combios_get_clock_info()
759 spll->reference_div = RBIOS16(pll_info + 0x1c); in radeon_combios_get_clock_info()
760 spll->pll_out_min = RBIOS32(pll_info + 0x1e); in radeon_combios_get_clock_info()
761 spll->pll_out_max = RBIOS32(pll_info + 0x22); in radeon_combios_get_clock_info()
764 spll->pll_in_min = RBIOS32(pll_info + 0x48); in radeon_combios_get_clock_info()
765 spll->pll_in_max = RBIOS32(pll_info + 0x4c); in radeon_combios_get_clock_info()
768 spll->pll_in_min = 40; in radeon_combios_get_clock_info()
769 spll->pll_in_max = 500; in radeon_combios_get_clock_info()
H A Dradeon_atombios.c1136 struct radeon_pll *spll = &rdev->clock.spll; in radeon_atom_get_clock_info() local
1189 spll->reference_freq = in radeon_atom_get_clock_info()
1192 spll->reference_freq = in radeon_atom_get_clock_info()
1194 spll->reference_div = 0; in radeon_atom_get_clock_info()
1196 spll->pll_out_min = in radeon_atom_get_clock_info()
1198 spll->pll_out_max = in radeon_atom_get_clock_info()
1202 if (spll->pll_out_min == 0) { in radeon_atom_get_clock_info()
1204 spll->pll_out_min = 64800; in radeon_atom_get_clock_info()
1206 spll->pll_out_min = 20000; in radeon_atom_get_clock_info()
1209 spll->pll_in_min = in radeon_atom_get_clock_info()
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H A Drv6xx_dpm.c164 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_output_stepping()
429 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_compute_count_for_delay()
552 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_engine_spread_spectrum()
841 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_bsp()
H A Drv740_dpm.c132 u32 reference_clock = rdev->clock.spll.reference_freq; in rv740_populate_sclk_value()
H A Drs780_dpm.c990 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_debugfs_print_current_performance_level()
1012 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_get_current_sclk()
H A Drv730_dpm.c52 u32 reference_clock = rdev->clock.spll.reference_freq; in rv730_populate_sclk_value()
H A Dradeon_kms.c381 *value = rdev->clock.spll.reference_freq * 10; in radeon_info_ioctl()
H A Dradeon_uvd.c969 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq; in radeon_uvd_calc_upll_dividers()
H A Drv770.c789 u32 reference_clock = rdev->clock.spll.reference_freq; in rv770_get_xclk()
H A Dci_dpm.c2024 u32 ref_clock = rdev->clock.spll.reference_freq; in ci_program_display_gap()
3044 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq; in ci_populate_smc_acpi_level()
3203 u32 reference_clock = rdev->clock.spll.reference_freq; in ci_calculate_sclk_params()
H A Dr600.c190 return rdev->clock.spll.reference_freq; in r600_get_xclk()
217 if (rdev->clock.spll.reference_freq == 10000) in r600_set_uvd_clocks()
H A Drv770_dpm.c505 u32 reference_clock = rdev->clock.spll.reference_freq; in rv770_populate_sclk_value()
H A Dradeon.h274 struct radeon_pll spll; member
H A Dni_dpm.c2010 u32 reference_clock = rdev->clock.spll.reference_freq; in ni_calculate_sclk_params()
H A Dsi.c1331 u32 reference_clock = rdev->clock.spll.reference_freq; in si_get_xclk()
H A Dsi_dpm.c4794 u32 reference_clock = rdev->clock.spll.reference_freq; in si_calculate_sclk_params()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Damdgpu_atomfirmware.c248 struct amdgpu_pll *spll = &adev->clock.spll; in amdgpu_atomfirmware_get_clock_info() local
286 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz); in amdgpu_atomfirmware_get_clock_info()
288 spll->reference_div = 0; in amdgpu_atomfirmware_get_clock_info()
289 spll->min_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
290 spll->max_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
291 spll->min_ref_div = 2; in amdgpu_atomfirmware_get_clock_info()
292 spll->max_ref_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
293 spll->min_feedback_div = 4; in amdgpu_atomfirmware_get_clock_info()
294 spll->max_feedback_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
295 spll->best_vco = 0; in amdgpu_atomfirmware_get_clock_info()
H A Damdgpu_atombios.c569 struct amdgpu_pll *spll = &adev->clock.spll; in amdgpu_atombios_get_clock_info() local
615 spll->reference_freq = in amdgpu_atombios_get_clock_info()
617 spll->reference_div = 0; in amdgpu_atombios_get_clock_info()
619 spll->pll_out_min = in amdgpu_atombios_get_clock_info()
621 spll->pll_out_max = in amdgpu_atombios_get_clock_info()
628 spll->pll_in_min = in amdgpu_atombios_get_clock_info()
630 spll->pll_in_max = in amdgpu_atombios_get_clock_info()
633 spll->min_post_div = 1; in amdgpu_atombios_get_clock_info()
634 spll->max_post_div = 1; in amdgpu_atombios_get_clock_info()
635 spll->min_ref_div = 2; in amdgpu_atombios_get_clock_info()
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H A Dsoc15.c208 u32 reference_clock = adev->clock.spll.reference_freq; in soc15_get_xclk()
H A Dcik.c842 u32 reference_clock = adev->clock.spll.reference_freq; in cik_get_xclk()
H A Dvi.c328 u32 reference_clock = adev->clock.spll.reference_freq; in vi_get_xclk()
H A Damdgpu.h357 struct amdgpu_pll spll; member
/dragonfly/sys/dev/drm/i915/
H A Dintel_dpll_mgr.h118 uint32_t spll; member
H A Dintel_dpll_mgr.c477 I915_WRITE(SPLL_CTL, pll->state.hw_state.spll); in hsw_ddi_spll_enable()
529 hw_state->spll = val; in hsw_ddi_spll_get_hw_state()
828 crtc_state->dpll_hw_state.spll = in hsw_get_dpll()
849 hw_state->wrpll, hw_state->spll); in hsw_dump_hw_state()

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