/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | amdgpu_uvd.c | 200 adev->uvd.fw = NULL; in amdgpu_uvd_sw_init() 260 (u64 *)&adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr); in amdgpu_uvd_sw_init() 269 adev->uvd.filp[i] = NULL; in amdgpu_uvd_sw_init() 278 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; in amdgpu_uvd_sw_init() 281 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; in amdgpu_uvd_sw_init() 284 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; in amdgpu_uvd_sw_init() 287 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; in amdgpu_uvd_sw_init() 316 release_firmware(adev->uvd.fw); in amdgpu_uvd_sw_fini() 406 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset, in amdgpu_uvd_resume() 440 adev->uvd.filp[i] = NULL; in amdgpu_uvd_free_handles() [all …]
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H A D | uvd_v7_0.c | 393 adev->uvd.harvest_config |= 1 << i; in uvd_v7_0_early_init() 401 adev->uvd.num_uvd_inst = 1; in uvd_v7_0_early_init() 405 adev->uvd.num_enc_rings = 1; in uvd_v7_0_early_init() 407 adev->uvd.num_enc_rings = 2; in uvd_v7_0_early_init() 456 ring = &adev->uvd.inst[j].ring; in uvd_v7_0_sw_init() 542 ring = &adev->uvd.inst[j].ring; in uvd_v7_0_hw_init() 624 adev->uvd.inst[i].ring.ready = false; in uvd_v7_0_hw_fini() 802 ring = &adev->uvd.inst[i].ring; in uvd_v7_0_sriov_start() 957 ring = &adev->uvd.inst[k].ring; in uvd_v7_0_start() 1845 adev->uvd.inst[i].ring.me = i; in uvd_v7_0_set_ring_funcs() [all …]
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H A D | uvd_v6_0.c | 67 (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16)); in uvd_v6_0_enc_support() 374 adev->uvd.num_uvd_inst = 1; in uvd_v6_0_early_init() 383 adev->uvd.num_enc_rings = 2; in uvd_v6_0_early_init() 420 adev->uvd.inst->irq.num_types = 1; in uvd_v6_0_sw_init() 421 adev->uvd.num_enc_rings = 0; in uvd_v6_0_sw_init() 426 ring = &adev->uvd.inst->ring; in uvd_v6_0_sw_init() 438 ring = &adev->uvd.inst->ring_enc[i]; in uvd_v6_0_sw_init() 856 ring = &adev->uvd.inst->ring_enc[0]; in uvd_v6_0_start() 863 ring = &adev->uvd.inst->ring_enc[1]; in uvd_v6_0_start() 1638 adev->uvd.inst->irq.num_types = adev->uvd.num_enc_rings + 1; in uvd_v6_0_set_irq_funcs() [all …]
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H A D | amdgpu_queue_mgr.c | 80 *out_ring = &adev->uvd.inst[0].ring; in amdgpu_identity_map() 86 *out_ring = &adev->uvd.inst[0].ring_enc[ring]; in amdgpu_identity_map() 246 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { in amdgpu_queue_mgr_map() 247 if (!(adev->uvd.harvest_config & (1 << i))) in amdgpu_queue_mgr_map() 255 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { in amdgpu_queue_mgr_map() 256 if (!(adev->uvd.harvest_config & (1 << i))) in amdgpu_queue_mgr_map() 260 adev->uvd.num_enc_rings * ip_num_rings; in amdgpu_queue_mgr_map()
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H A D | uvd_v5_0.c | 93 adev->uvd.num_uvd_inst = 1; in uvd_v5_0_early_init() 116 ring = &adev->uvd.inst->ring; in uvd_v5_0_sw_init() 153 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v5_0_hw_init() 213 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v5_0_hw_fini() 262 lower_32_bits(adev->uvd.inst->gpu_addr)); in uvd_v5_0_mc_resume() 264 upper_32_bits(adev->uvd.inst->gpu_addr)); in uvd_v5_0_mc_resume() 296 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v5_0_start() 607 amdgpu_fence_process(&adev->uvd.inst->ring); in uvd_v5_0_process_interrupt() 881 adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs; in uvd_v5_0_set_ring_funcs() 891 adev->uvd.inst->irq.num_types = 1; in uvd_v5_0_set_irq_funcs() [all …]
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H A D | amdgpu_kms.c | 172 fw_info->ver = adev->uvd.fw_version; in amdgpu_firmware_info() 329 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { in amdgpu_info_ioctl() 330 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_info_ioctl() 332 ring_mask |= adev->uvd.inst[i].ring.ready; in amdgpu_info_ioctl() 346 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { in amdgpu_info_ioctl() 347 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_info_ioctl() 349 for (j = 0; j < adev->uvd.num_enc_rings; j++) in amdgpu_info_ioctl() 350 ring_mask |= adev->uvd.inst[i].ring_enc[j].ready << j; in amdgpu_info_ioctl() 705 handle.uvd_max_handles = adev->uvd.max_handles; in amdgpu_info_ioctl()
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H A D | amdgpu_fence.c | 387 index = ALIGN(adev->uvd.fw->datasize, 8); in amdgpu_fence_driver_start_ring() 388 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index; in amdgpu_fence_driver_start_ring() 389 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index; in amdgpu_fence_driver_start_ring()
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H A D | amdgpu_uvd.h | 37 …(AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->…
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H A D | amdgpu.h | 1509 struct amdgpu_uvd uvd; member
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/dragonfly/sys/dev/drm/radeon/ |
H A D | radeon_uvd.c | 189 NULL, &rdev->uvd.vcpu_bo); in radeon_uvd_init() 203 &rdev->uvd.gpu_addr); in radeon_uvd_init() 211 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr); in radeon_uvd_init() 221 rdev->uvd.filp[i] = NULL; in radeon_uvd_init() 222 rdev->uvd.img_size[i] = 0; in radeon_uvd_init() 232 if (rdev->uvd.vcpu_bo == NULL) in radeon_uvd_fini() 253 if (rdev->uvd.vcpu_bo == NULL) in radeon_uvd_suspend() 273 rdev->uvd.filp[i] = NULL; in radeon_uvd_suspend() 286 if (rdev->uvd.vcpu_bo == NULL) in radeon_uvd_resume() 294 ptr = rdev->uvd.cpu_addr; in radeon_uvd_resume() [all …]
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H A D | uvd_v4_2.c | 46 if (rdev->uvd.fw_header_present) in uvd_v4_2_resume() 47 addr = (rdev->uvd.gpu_addr + 0x200) >> 3; in uvd_v4_2_resume() 49 addr = rdev->uvd.gpu_addr >> 3; in uvd_v4_2_resume() 62 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v4_2_resume() 67 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v4_2_resume() 71 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v4_2_resume() 74 if (rdev->uvd.fw_header_present) in uvd_v4_2_resume() 75 WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles); in uvd_v4_2_resume()
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H A D | uvd_v2_2.c | 113 addr = rdev->uvd.gpu_addr >> 3; in uvd_v2_2_resume() 125 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v2_2_resume() 130 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v2_2_resume() 134 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v2_2_resume()
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H A D | uvd_v1_0.c | 121 addr = (rdev->uvd.gpu_addr >> 3) + 16; in uvd_v1_0_resume() 133 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v1_0_resume() 138 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v1_0_resume() 142 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v1_0_resume() 145 WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr)); in uvd_v1_0_resume()
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H A D | radeon_drv.c | 322 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); 323 module_param_named(uvd, radeon_uvd, int, 0444);
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H A D | radeon_fence.c | 843 rdev->fence_drv[ring].cpu_addr = (void*)((uint8_t*)rdev->uvd.cpu_addr + index); in radeon_fence_driver_start_ring() 844 rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index; in radeon_fence_driver_start_ring()
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H A D | radeon.h | 2394 struct radeon_uvd uvd; member
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/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/ |
H A D | smu10_hwmgr.h | 112 uint32_t uvd : 1; member
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H A D | smu8_hwmgr.h | 135 uint32_t uvd : 1; member
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