Searched refs:vclk_div (Results 1 – 5 of 5) sorted by relevance
/dragonfly/sys/dev/drm/radeon/ |
H A D | radeon_uvd.c | 979 unsigned vclk_div, dclk_div, score; in radeon_uvd_calc_upll_dividers() local 990 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, in radeon_uvd_calc_upll_dividers() 992 if (vclk_div > pd_max) in radeon_uvd_calc_upll_dividers() 1002 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers() 1007 *optimal_vclk_div = vclk_div; in radeon_uvd_calc_upll_dividers()
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H A D | rv770.c | 46 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks() local 66 &fb_div, &vclk_div, &dclk_div); in rv770_set_uvd_clocks() 71 vclk_div -= 1; in rv770_set_uvd_clocks() 94 UPLL_SW_HILEN(vclk_div >> 1) | in rv770_set_uvd_clocks() 95 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | in rv770_set_uvd_clocks()
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H A D | r600.c | 195 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; in r600_set_uvd_clocks() local 224 &fb_div, &vclk_div, &dclk_div); in r600_set_uvd_clocks() 251 UPLL_SW_HILEN(vclk_div >> 1) | in r600_set_uvd_clocks() 252 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | in r600_set_uvd_clocks()
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H A D | evergreen.c | 1177 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in evergreen_set_uvd_clocks() local 1196 &fb_div, &vclk_div, &dclk_div); in evergreen_set_uvd_clocks() 1235 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), in evergreen_set_uvd_clocks()
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H A D | si.c | 6994 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks() local 7012 &fb_div, &vclk_div, &dclk_div); in si_set_uvd_clocks() 7053 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), in si_set_uvd_clocks()
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