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Searched refs:vmid (Results 1 – 25 of 48) sorted by relevance

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/dragonfly/sys/dev/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v9.c100 unsigned int vmid);
137 uint8_t vmid);
139 uint8_t vmid);
316 (1U << vmid))) in kgd_set_pasid_vmid_mapping()
768 + vmid); in get_atc_vmid_pasid_mapping_valid()
779 + vmid); in get_atc_vmid_pasid_mapping_pasid()
829 (1 << vmid))) in write_vmid_invalidate_request()
834 (1 << vmid))) in write_vmid_invalidate_request()
871 int vmid; in invalidate_tlbs() local
880 for (vmid = 0; vmid < 16; vmid++) { in invalidate_tlbs()
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H A Damdgpu_amdkfd_gfx_v8.c59 unsigned int vmid);
96 uint8_t vmid);
98 uint8_t vmid);
101 uint64_t va, uint32_t vmid);
236 lock_srbm(kgd, 0, 0, 0, vmid); in kgd_program_sh_mem_settings()
247 unsigned int vmid) in kgd_set_pasid_vmid_mapping() argument
703 uint8_t vmid) in get_atc_vmid_pasid_mapping_valid() argument
713 uint8_t vmid) in get_atc_vmid_pasid_mapping_pasid() argument
773 lock_srbm(kgd, 0, 0, 0, vmid); in set_scratch_backing_va()
850 int vmid; in invalidate_tlbs() local
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H A Dgmc_v9_0.c269 entry->src_id, entry->ring_id, entry->vmid, in gmc_v9_0_process_interrupt()
294 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid) in gmc_v9_0_get_invalidate_req() argument
300 PER_VMID_INVALIDATE_REQ, 1 << vmid); in gmc_v9_0_get_invalidate_req()
329 uint32_t vmid) in gmc_v9_0_flush_gpu_tlb() argument
339 u32 tmp = gmc_v9_0_get_invalidate_req(vmid); in gmc_v9_0_flush_gpu_tlb()
346 tmp &= 1 << vmid; in gmc_v9_0_flush_gpu_tlb()
357 tmp &= 1 << vmid; in gmc_v9_0_flush_gpu_tlb()
372 unsigned vmid, uint64_t pd_addr) in gmc_v9_0_emit_flush_gpu_tlb() argument
376 uint32_t req = gmc_v9_0_get_invalidate_req(vmid); in gmc_v9_0_emit_flush_gpu_tlb()
391 req, 1 << vmid); in gmc_v9_0_emit_flush_gpu_tlb()
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H A Damdgpu_gmc.h54 uint32_t vmid);
56 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
59 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid,
H A Dgmc_v7_0.c435 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v7_0_flush_gpu_tlb()
439 unsigned vmid, uint64_t pd_addr) in gmc_v7_0_emit_flush_gpu_tlb() argument
443 if (vmid < 8) in gmc_v7_0_emit_flush_gpu_tlb()
444 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; in gmc_v7_0_emit_flush_gpu_tlb()
446 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; in gmc_v7_0_emit_flush_gpu_tlb()
450 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v7_0_emit_flush_gpu_tlb()
458 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); in gmc_v7_0_emit_pasid_mapping()
772 protections, vmid, pasid, addr, in gmc_v7_0_vm_decode_fault()
1284 u32 addr, status, mc_client, vmid; in gmc_v7_0_process_interrupt() local
1311 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) in gmc_v7_0_process_interrupt()
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H A Dvcn_v1_0.c996 unsigned vmid, bool ctx_switch) in vcn_v1_0_dec_ring_emit_ib() argument
1002 amdgpu_ring_write(ring, vmid); in vcn_v1_0_dec_ring_emit_ib()
1036 unsigned vmid, uint64_t pd_addr) in vcn_v1_0_dec_ring_emit_vm_flush() argument
1044 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; in vcn_v1_0_dec_ring_emit_vm_flush()
1156 amdgpu_ring_write(ring, vmid); in vcn_v1_0_enc_ring_emit_ib()
1173 unsigned int vmid, uint64_t pd_addr) in vcn_v1_0_enc_ring_emit_vm_flush() argument
1351 unsigned vmid, bool ctx_switch) in vcn_v1_0_jpeg_ring_emit_ib() argument
1357 amdgpu_ring_write(ring, (vmid | (vmid << 4))); in vcn_v1_0_jpeg_ring_emit_ib()
1361 amdgpu_ring_write(ring, (vmid | (vmid << 4))); in vcn_v1_0_jpeg_ring_emit_ib()
1431 unsigned vmid, uint64_t pd_addr) in vcn_v1_0_jpeg_ring_emit_vm_flush() argument
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H A Dgmc_v8_0.c635 uint32_t vmid) in gmc_v8_0_flush_gpu_tlb() argument
638 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v8_0_flush_gpu_tlb()
642 unsigned vmid, uint64_t pd_addr) in gmc_v8_0_emit_flush_gpu_tlb() argument
646 if (vmid < 8) in gmc_v8_0_emit_flush_gpu_tlb()
647 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; in gmc_v8_0_emit_flush_gpu_tlb()
649 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; in gmc_v8_0_emit_flush_gpu_tlb()
661 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); in gmc_v8_0_emit_pasid_mapping()
1016 protections, vmid, pasid, addr, in gmc_v8_0_vm_decode_fault()
1456 u32 addr, status, mc_client, vmid; in gmc_v8_0_process_interrupt() local
1495 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) in gmc_v8_0_process_interrupt()
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H A Damdgpu_ib.c154 if (vm && !job->vmid) { in amdgpu_ib_schedule()
220 amdgpu_ring_emit_ib(ring, ib, job ? job->vmid : 0, in amdgpu_ib_schedule()
245 if (job && job->vmid) in amdgpu_ib_schedule()
246 amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vmid); in amdgpu_ib_schedule()
H A Damdgpu_amdkfd.c448 uint32_t vmid, uint64_t gpu_addr, in amdgpu_amdkfd_submit_ib() argument
485 job->vmid = vmid; in amdgpu_amdkfd_submit_ib()
513 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) in amdgpu_amdkfd_is_kfd_vmid() argument
516 if ((1 << vmid) & compute_vmid_bitmap) in amdgpu_amdkfd_is_kfd_vmid()
H A Duvd_v6_0.c1015 unsigned vmid, bool ctx_switch) in uvd_v6_0_ring_emit_ib() argument
1018 amdgpu_ring_write(ring, vmid); in uvd_v6_0_ring_emit_ib()
1037 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch) in uvd_v6_0_enc_ring_emit_ib() argument
1040 amdgpu_ring_write(ring, vmid); in uvd_v6_0_enc_ring_emit_ib()
1058 unsigned vmid, uint64_t pd_addr) in uvd_v6_0_ring_emit_vm_flush() argument
1060 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); in uvd_v6_0_ring_emit_vm_flush()
1067 amdgpu_ring_write(ring, 1 << vmid); /* mask */ in uvd_v6_0_ring_emit_vm_flush()
1118 unsigned int vmid, uint64_t pd_addr) in uvd_v6_0_enc_ring_emit_vm_flush() argument
1121 amdgpu_ring_write(ring, vmid); in uvd_v6_0_enc_ring_emit_vm_flush()
1125 amdgpu_ring_write(ring, vmid); in uvd_v6_0_enc_ring_emit_vm_flush()
H A Damdgpu_ring.h133 unsigned vmid, bool ctx_switch);
137 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
140 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
H A Damdgpu_amdkfd.h120 uint32_t vmid, uint64_t gpu_addr,
128 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);
H A Dcik.h30 u32 me, u32 pipe, u32 queue, u32 vmid);
H A Dvi.h30 u32 me, u32 pipe, u32 queue, u32 vmid);
H A Damdgpu.h1729 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid)) argument
1730 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((… argument
1731 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping(… argument
1745 #define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib), (vmid), (c)) argument
1747 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) argument
H A Duvd_v7_0.c1300 unsigned vmid, bool ctx_switch) in uvd_v7_0_ring_emit_ib() argument
1306 amdgpu_ring_write(ring, vmid); in uvd_v7_0_ring_emit_ib()
1328 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch) in uvd_v7_0_enc_ring_emit_ib() argument
1331 amdgpu_ring_write(ring, vmid); in uvd_v7_0_enc_ring_emit_ib()
1373 unsigned vmid, uint64_t pd_addr) in uvd_v7_0_ring_emit_vm_flush() argument
1378 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); in uvd_v7_0_ring_emit_vm_flush()
1381 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; in uvd_v7_0_ring_emit_vm_flush()
1416 unsigned int vmid, uint64_t pd_addr) in uvd_v7_0_enc_ring_emit_vm_flush() argument
1420 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); in uvd_v7_0_enc_ring_emit_vm_flush()
1423 uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2, in uvd_v7_0_enc_ring_emit_vm_flush()
H A Dvce_v3_0.c841 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch) in vce_v3_0_ring_emit_ib() argument
844 amdgpu_ring_write(ring, vmid); in vce_v3_0_ring_emit_ib()
851 unsigned int vmid, uint64_t pd_addr) in vce_v3_0_emit_vm_flush() argument
854 amdgpu_ring_write(ring, vmid); in vce_v3_0_emit_vm_flush()
858 amdgpu_ring_write(ring, vmid); in vce_v3_0_emit_vm_flush()
H A Damdgpu_ids.c458 job->vmid = id - id_mgr->ids; in amdgpu_vmid_grab()
523 unsigned vmid) in amdgpu_vmid_reset() argument
526 struct amdgpu_vmid *id = &id_mgr->ids[vmid]; in amdgpu_vmid_reset()
H A Dsoc15.h50 u32 me, u32 pipe, u32 queue, u32 vmid);
H A Damdgpu_ih.h69 unsigned vmid; member
H A Damdgpu_job.h50 unsigned vmid; member
H A Damdgpu_ids.h90 unsigned vmid);
H A Damdgpu_vce.h69 unsigned vmid, bool ctx_switch);
H A Dvce_v4_0.c950 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch) in vce_v4_0_ring_emit_ib() argument
953 amdgpu_ring_write(ring, vmid); in vce_v4_0_ring_emit_ib()
986 unsigned int vmid, uint64_t pd_addr) in vce_v4_0_emit_vm_flush() argument
990 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); in vce_v4_0_emit_vm_flush()
993 vce_v4_0_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2, in vce_v4_0_emit_vm_flush()
/dragonfly/sys/dev/drm/amd/include/
H A Dkgd_kfd_interface.h52 uint32_t vmid; member
309 void (*program_sh_mem_settings)(struct kgd_dev *kgd, uint32_t vmid,
314 unsigned int vmid);
360 uint8_t vmid);
363 uint8_t vmid);
368 uint64_t va, uint32_t vmid);
382 uint32_t vmid, uint32_t page_table_base);
398 int (*invalidate_tlbs_vmid)(struct kgd_dev *kgd, uint16_t vmid);
401 uint32_t vmid, uint64_t gpu_addr,

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