/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
H A D | LoongArchISelDAGToDAG.cpp | 233 const APInt &AndMask = N->getConstantOperandAPInt(1); in selectShiftMask() local 238 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); in selectShiftMask() 240 if (ShMask.isSubsetOf(AndMask)) { in selectShiftMask() 248 if (ShMask.isSubsetOf(AndMask | Known.Zero)) { in selectShiftMask()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | AMDGPUInstPrinter.cpp | 1513 static void printSwizzleBitmask(const uint16_t AndMask, in printSwizzleBitmask() argument 1519 uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask; in printSwizzleBitmask() 1520 uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask; in printSwizzleBitmask() 1570 uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK; in printSwizzle() local 1574 if (AndMask == BITMASK_MAX && OrMask == 0 && llvm::popcount(XorMask) == 1) { in printSwizzle() 1581 } else if (AndMask == BITMASK_MAX && OrMask == 0 && XorMask > 0 && in printSwizzle() 1591 uint16_t GroupSize = BITMASK_MAX - AndMask + 1; in printSwizzle() 1607 printSwizzleBitmask(AndMask, OrMask, XorMask, O); in printSwizzle()
|
/freebsd/lib/libvgl/ |
H A D | vgl.h | 128 void VGLMouseSetImage(VGLBitmap *AndMask, VGLBitmap *OrMask);
|
H A D | mouse.c | 252 VGLMouseSetImage(VGLBitmap *AndMask, VGLBitmap *OrMask) in VGLMouseSetImage() argument 258 VGLMouseAndMask = AndMask; in VGLMouseSetImage()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
H A D | RISCVInstructionSelector.cpp | 180 APInt AndMask; in selectShiftMask() local 182 if (mi_match(ShAmtReg, MRI, m_GAnd(m_Reg(AndSrcReg), m_ICst(AndMask)))) { in selectShiftMask() 183 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); in selectShiftMask() 184 if (ShMask.isSubsetOf(AndMask)) { in selectShiftMask() 190 if (ShMask.isSubsetOf(AndMask | Known.Zero)) in selectShiftMask()
|
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineSelect.cpp | 134 APInt AndMask; in foldSelectICmpAnd() local 146 AndMask = *AndRHS; in foldSelectICmpAnd() 148 Pred, V, AndMask)) { in foldSelectICmpAnd() 150 if (!AndMask.isPowerOf2()) in foldSelectICmpAnd() 168 if (TC.getBitWidth() != AndMask.getBitWidth() || (TC ^ FC) != AndMask) in foldSelectICmpAnd() 175 V = Builder.CreateAnd(V, ConstantInt::get(SelType, AndMask)); in foldSelectICmpAnd() 203 unsigned AndZeros = AndMask.logBase2(); in foldSelectICmpAnd() 207 V = Builder.CreateAnd(V, ConstantInt::get(V->getType(), AndMask)); in foldSelectICmpAnd()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 745 uint64_t AndMask = MaskNode->getZExtValue(); in detectOrAndInsertion() local 746 if (InsertMask & AndMask) in detectOrAndInsertion() 752 if (Used != (AndMask | InsertMask)) { in detectOrAndInsertion() 754 if (Used != (AndMask | InsertMask | Known.Zero.getZExtValue())) in detectOrAndInsertion()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64FrameLowering.cpp | 740 const uint64_t AndMask = ~(MaxAlign - 1); in allocateStackSpace() local 755 .addImm(AArch64_AM::encodeLogicalImmediate(AndMask, 64)) in allocateStackSpace() 814 .addImm(AArch64_AM::encodeLogicalImmediate(AndMask, 64)) in allocateStackSpace() 843 .addImm(AArch64_AM::encodeLogicalImmediate(AndMask, 64)) in allocateStackSpace() 2026 uint64_t AndMask = ~(MFI.getMaxAlign().value() - 1); in emitPrologue() local 2029 .addImm(AArch64_AM::encodeLogicalImmediate(AndMask, 64)); in emitPrologue()
|
H A D | AArch64ISelDAGToDAG.cpp | 727 APInt AndMask = RHSC->getAPIntValue(); in SelectShiftedRegisterFromAnd() local 729 if (!AndMask.isShiftedMask(LowZBits, MaskLen)) in SelectShiftedRegisterFromAnd() 815 uint64_t AndMask = CSD->getZExtValue(); in getExtendTypeForNode() local 817 switch (AndMask) { in getExtendTypeForNode() 2431 uint64_t AndMask = 0; in isSeveralBitsExtractOpFromShr() local 2432 if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, AndMask)) in isSeveralBitsExtractOpFromShr() 2442 if (!isMask_64(AndMask >> SrlImm)) in isSeveralBitsExtractOpFromShr() 2447 MSB = llvm::Log2_64(AndMask); in isSeveralBitsExtractOpFromShr()
|
H A D | AArch64ISelLowering.cpp | 19091 uint64_t AndMask = CSD->getZExtValue(); in isExtendOrShiftOperand() local 19092 return AndMask == 0xff || AndMask == 0xffff || AndMask == 0xffffffff; in isExtendOrShiftOperand()
|
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/ |
H A D | DataFlowSanitizer.cpp | 282 uint64_t AndMask; member 1902 uint64_t AndMask = MapParams->AndMask; in getShadowOffset() local 1903 if (AndMask) in getShadowOffset() 1905 IRB.CreateAnd(OffsetLong, ConstantInt::get(IntptrTy, ~AndMask)); in getShadowOffset()
|
H A D | MemorySanitizer.cpp | 380 uint64_t AndMask; member 974 CustomMapParams.AndMask = ClAndMask; in initializeModule() 1696 if (uint64_t AndMask = MS.MapParams->AndMask) in getShadowPtrOffset() local 1697 OffsetLong = IRB.CreateAnd(OffsetLong, constToIntPtr(IntptrTy, ~AndMask)); in getShadowPtrOffset()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.h | 976 const APInt &AndMask) const override;
|
H A D | RISCVISelDAGToDAG.cpp | 2558 const APInt &AndMask = ShAmt.getConstantOperandAPInt(1); in selectShiftMask() local 2563 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); in selectShiftMask() 2565 if (ShMask.isSubsetOf(AndMask)) { in selectShiftMask() 2571 if (!ShMask.isSubsetOf(AndMask | Known.Zero)) in selectShiftMask()
|
H A D | RISCVISelLowering.cpp | 20384 EVT VT, const APInt &AndMask) const { in shouldFoldSelectWithSingleBitTest() 20386 return !Subtarget.hasStdExtZbs() && AndMask.ugt(1024); in shouldFoldSelectWithSingleBitTest() 20387 return TargetLowering::shouldFoldSelectWithSingleBitTest(VT, AndMask); in shouldFoldSelectWithSingleBitTest()
|
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetLowering.h | 850 const std::optional<APInt> &AndMask) const { in preferedOpcodeForCmpEqPiecesOfOperand() argument 3264 const APInt &AndMask) const { in shouldFoldSelectWithSingleBitTest() argument 3265 unsigned ShCt = AndMask.getBitWidth() - 1; in shouldFoldSelectWithSingleBitTest()
|
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
H A D | Local.cpp | 3753 const APInt &AndMask = *C; in collectBitParts() local 3757 unsigned NumMaskedBits = AndMask.popcount(); in collectBitParts() 3769 if (AndMask[BitIdx] == 0) in collectBitParts()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.h | 1144 const std::optional<APInt> &AndMask) const override;
|
H A D | X86ISelLowering.cpp | 3276 const APInt &ShiftOrRotateAmt, const std::optional<APInt> &AndMask) const { in preferedOpcodeForCmpEqPiecesOfOperand() 3298 assert(AndMask.has_value() && "Null andmask when querying about shift+and"); in preferedOpcodeForCmpEqPiecesOfOperand() 3314 return AndMask->getSignificantBits() > 32 ? (unsigned)ISD::SRL in preferedOpcodeForCmpEqPiecesOfOperand() 3326 return AndMask->getSignificantBits() > 33 ? (unsigned)ISD::SHL : ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 7647 encodeBitmaskPerm(const unsigned AndMask, in encodeBitmaskPerm() argument 7653 (AndMask << BITMASK_AND_SHIFT) | in encodeBitmaskPerm() 7799 unsigned AndMask = 0; in parseSwizzleBitmaskPerm() local 7815 AndMask |= Mask; in parseSwizzleBitmaskPerm() 7818 AndMask |= Mask; in parseSwizzleBitmaskPerm() 7824 Imm = encodeBitmaskPerm(AndMask, OrMask, XorMask); in parseSwizzleBitmaskPerm()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 5373 auto AndMask = B.buildConstant(S32, 0x0000ffff); in legalizePointerAsRsrcIntrin() local 5374 auto Masked = B.buildAnd(S32, HighHalf, AndMask); in legalizePointerAsRsrcIntrin()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64InstructionSelector.cpp | 7502 uint64_t AndMask = *MaybeAndMask; in getExtendTypeForInst() local 7503 switch (AndMask) { in getExtendTypeForInst()
|
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 25672 SmallVector<SDValue, 16> AndMask(NumElts, DAG.getUNDEF(IntSVT)); in visitVECTOR_SHUFFLE() local 25675 AndMask[I] = Mask[I] == I ? AllOnesElt : ZeroElt; in visitVECTOR_SHUFFLE() 25687 DAG.getBuildVector(IntVT, DL, AndMask))); in visitVECTOR_SHUFFLE() 27309 const APInt &AndMask = ConstAndRHS->getAPIntValue(); in SimplifySelectCC() local 27310 if (TLI.shouldFoldSelectWithSingleBitTest(VT, AndMask)) { in SimplifySelectCC() 27311 unsigned ShCt = AndMask.getBitWidth() - 1; in SimplifySelectCC() 27313 DAG.getConstant(AndMask.countl_zero(), SDLoc(AndLHS), in SimplifySelectCC()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 17721 uint32_t AndMask = static_cast<uint32_t>(AndMaskNode->getZExtValue()); in PerformShiftCombine() local 17723 if (AndMask == 255 || AndMask == 65535) in PerformShiftCombine() 17725 if (isMask_32(AndMask)) { in PerformShiftCombine() 17726 uint32_t MaskedBits = llvm::countl_zero(AndMask); in PerformShiftCombine()
|