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Searched refs:Div (Results 1 – 25 of 58) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp412 IRBuilder<> Builder(Div); in expandDivision()
426 Div->eraseFromParent(); in expandDivision()
435 Div = BO; in expandDivision()
443 Div->dropAllReferences(); in expandDivision()
444 Div->eraseFromParent(); in expandDivision()
569 IRBuilder<> Builder(Div); in expandDivisionUpTo32Bits()
589 Div->dropAllReferences(); in expandDivisionUpTo32Bits()
590 Div->eraseFromParent(); in expandDivisionUpTo32Bits()
615 IRBuilder<> Builder(Div); in expandDivisionUpTo64Bits()
635 Div->dropAllReferences(); in expandDivisionUpTo64Bits()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/Utils/
H A DIntegerDivision.h41 bool expandDivision(BinaryOperator* Div);
62 bool expandDivisionUpTo32Bits(BinaryOperator *Div);
68 bool expandDivisionUpTo64Bits(BinaryOperator *Div);
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp367 int64_t Div = 0; in generateInstSeq() local
372 Div = 3; in generateInstSeq()
375 Div = 5; in generateInstSeq()
378 Div = 9; in generateInstSeq()
382 if (Div > 0) { in generateInstSeq()
383 generateInstSeqImpl(Val / Div, STI, TmpSeq); in generateInstSeq()
392 Div = 0; in generateInstSeq()
394 Div = 3; in generateInstSeq()
397 Div = 5; in generateInstSeq()
400 Div = 9; in generateInstSeq()
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/freebsd/contrib/llvm-project/clang/lib/CodeGen/Targets/
H A DNVPTX.cpp141 const unsigned Div = std::min<unsigned>(MaxSize, Alignment); in coerceToIntArrayWithLimit() local
142 llvm::Type *IntType = llvm::Type::getIntNTy(getVMContext(), Div); in coerceToIntArrayWithLimit()
143 const uint64_t NumElements = (Size + Div - 1) / Div; in coerceToIntArrayWithLimit()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DDivRemPairs.cpp56 Instruction *Div; in matchExpandedRem() local
61 m_Instruction(Div)), in matchExpandedRem()
66 M.Key.SignedOp = Div->getOpcode() == Instruction::SDiv; in matchExpandedRem()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineMulDivRem.cpp377 BinaryOperator *Div = dyn_cast<BinaryOperator>(Op0); in visitMul() local
378 if (!Div || (Div->getOpcode() != Instruction::UDiv && in visitMul()
379 Div->getOpcode() != Instruction::SDiv)) { in visitMul()
381 Div = dyn_cast<BinaryOperator>(Op1); in visitMul()
384 if (Div && Div->hasOneUse() && in visitMul()
385 (Div->getOperand(1) == Y || Div->getOperand(1) == Neg) && in visitMul()
386 (Div->getOpcode() == Instruction::UDiv || in visitMul()
387 Div->getOpcode() == Instruction::SDiv)) { in visitMul()
388 Value *X = Div->getOperand(0), *DivOp1 = Div->getOperand(1); in visitMul()
391 if (Div->isExact()) { in visitMul()
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H A DInstCombineCompares.cpp2613 BinaryOperator *Div, in foldICmpDivConstant() argument
2616 Value *X = Div->getOperand(0); in foldICmpDivConstant()
2617 Value *Y = Div->getOperand(1); in foldICmpDivConstant()
2618 Type *Ty = Div->getType(); in foldICmpDivConstant()
2619 bool DivIsSigned = Div->getOpcode() == Instruction::SDiv; in foldICmpDivConstant()
2629 if (Cmp.isEquality() && Div->hasOneUse() && C.isSignBitSet() && in foldICmpDivConstant()
2678 APInt RangeSize = Div->isExact() ? APInt(C2->getBitWidth(), 1) : *C2; in foldICmpDivConstant()
2719 if (Div->isExact()) in foldICmpDivConstant()
4376 Instruction *Div; in foldMultiplicationOverflowCheck() local
4382 m_Instruction(Div)), in foldMultiplicationOverflowCheck()
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/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DConstantFold.cpp1686 Constant *Div = in ConstantFoldGetElementPtr() local
1691 assert(NewIdxs[i] != nullptr && Div != nullptr && "Should have folded"); in ConstantFoldGetElementPtr()
1695 Div->getType()->getScalarSizeInBits()); in ConstantFoldGetElementPtr()
1700 Type *ExtendedTy = Type::getIntNTy(Div->getContext(), CommonExtendedWidth); in ConstantFoldGetElementPtr()
1712 if (!Div->getType()->isIntOrIntVectorTy(CommonExtendedWidth)) in ConstantFoldGetElementPtr()
1713 Div = ConstantFoldCastInstruction(Instruction::SExt, Div, ExtendedTy); in ConstantFoldGetElementPtr()
1715 assert(PrevIdx && Div && "Should have folded"); in ConstantFoldGetElementPtr()
1716 NewIdxs[i - 1] = ConstantExpr::getAdd(PrevIdx, Div); in ConstantFoldGetElementPtr()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX.td43 def THXT8XUnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mul/Div/Sqrt
70 // Div
161 // FP Mul, Div, Sqrt
238 // Div
H A DAArch64SchedA53.td48 def A53UnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt
72 // Div
134 // FP Mul, Div, Sqrt
195 // Div
H A DAArch64SchedA55.td56 def CortexA55UnitFPDIV : ProcResource<1> { let BufferSize = 0; } // FP Div/SQRT, 64/128
77 // Div
187 // FP Mul, Div, Sqrt. Div/Sqrt are not pipelined
252 // Div
H A DAArch64SchedA510.td59 …def CortexA510UnitVMC : ProcResource<1>; // SIMD/FP/SVE multicycle instrs (e.g Div, SQRT, c…
79 // Div
200 // FP Mul, Div, Sqrt. Div/Sqrt are not pipelined
237 // Div
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETailPredication.cpp327 const SCEV *Div = SE->getUDivExpr( in IsSafeActiveMask() local
331 const SCEV *Sub = SE->getMinusSCEV(SE->getBackedgeTakenCount(L), Div); in IsSafeActiveMask()
H A DARMScheduleM4.td105 // Most FP instructions are single-cycle latency, except MAC's, Div's and Sqrt's.
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPrepareFunctions.cpp229 Value *Div = IRB.CreateUDiv(Mul, UMulFunc->getArg(0)); in buildUMulWithOverflowFunc() local
230 Value *Overflow = IRB.CreateICmpNE(UMulFunc->getArg(0), Div); in buildUMulWithOverflowFunc()
/freebsd/contrib/llvm-project/clang/include/clang/AST/
H A DCommentHTMLTags.td20 def Div : Tag<"div">;
H A DStmtVisitor.h127 BINOP_FALLBACK(Mul) BINOP_FALLBACK(Div) BINOP_FALLBACK(Rem) in BINOP_FALLBACK()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCExpr.h489 Div, ///< Signed division. enumerator
540 return create(Div, LHS, RHS, Ctx); in createDiv()
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCExpr.cpp140 case MCBinaryExpr::Div: OS << '/'; break; in print()
1003 case MCBinaryExpr::Div: in evaluateAsRelocatableImpl()
1013 if (ABE->getOpcode() == MCBinaryExpr::Div) in evaluateAsRelocatableImpl()
H A DMCWin64EH.cpp265 const MCSymbol *RHS, int Div) { in GetSubDivExpr() argument
270 if (Div != 1) in GetSubDivExpr()
271 Expr = MCBinaryExpr::createDiv(Expr, MCConstantExpr::create(Div, Context), in GetSubDivExpr()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DLoopCacheAnalysis.cpp432 const SCEV *Div = SE.getUDivExactExpr(AccessFn, ElemSize); in delinearize() local
433 Subscripts.push_back(Div); in delinearize()
H A DBranchProbabilityInfo.cpp501 uint32_t Div = static_cast<uint32_t>( in calcMetadataWeights() local
503 BP[I] = BranchProbability::getRaw(Div); in calcMetadataWeights()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCodeGenPrepare.cpp1294 Value *Div = Builder.CreateAdd(IQ, JQ); in expandDivRem24Impl() local
1296 Value *Res = Div; in expandDivRem24Impl()
1299 Value *Rem = Builder.CreateMul(Div, Den); in expandDivRem24Impl()
1613 for (BinaryOperator *Div : Div64ToExpand) { in visitBinaryOperator()
1614 expandDivRem64(*Div); in visitBinaryOperator()
H A DAMDGPUISelLowering.cpp1958 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq); in LowerDIVREM24() local
1961 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS); in LowerDIVREM24()
1968 Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize); in LowerDIVREM24()
1972 Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask); in LowerDIVREM24()
1976 return DAG.getMergeValues({ Div, Rem }, DL); in LowerDIVREM24()
2144 Results.push_back(Div); in LowerUDIVREM64()
2293 SDValue Rem = Div.getValue(1); in LowerSDIVREM()
2295 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign); in LowerSDIVREM()
2298 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign); in LowerSDIVREM()
2302 Div, in LowerSDIVREM()
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/freebsd/contrib/llvm-project/clang/lib/AST/Interp/
H A DOpcodes.td523 def Div : IntegerOpcode;

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