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Searched refs:EVEX (Results 1 – 25 of 27) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrAVX512.td663 EVEX, VVVV, EVEX_CD8<32, CD8VT1>,
828 // smaller extract to enable EVEX->VEX.
861 // smaller extract to enable EVEX->VEX.
2655 EVEX, TB, PD;
2664 EVEX, TB;
2678 EVEX, TB, PD, REX_W;
2680 EVEX, TB, XD;
2682 EVEX, TB, REX_W;
2684 EVEX, TB, XD, REX_W;
9611 EVEX, Sched<[sched]>;
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H A DX86InstrPredicates.td12 // EVEX. Not all X86 instructions are extended for EGPR. The following is an
19 // * EVEX space
20 // All instructions in the EVEX space can access the EGPR in their
24 // the REX2/EVEX prefix when EGPR is used, i.e. the opcode and opcode name are
29 // promoted into EVEX space. Encoding space changes after the promotion, opcode
H A DX86CompressEVEX.cpp211 if ((TSFlags & X86II::EncodingMask) != X86II::EVEX) in CompressEVEXImpl()
258 case X86II::EVEX: in CompressEVEXImpl()
H A DX86InstrVMX.td27 EVEX, NoCD8, T_MAP4, XS, Requires<[In64BitMode]>;
38 EVEX, NoCD8, T_MAP4, XS, Requires<[In64BitMode]>;
H A DX86InstrMisc.td168 []>, EVEX, VVVV, EVEX_B, T_MAP4;
171 []>, EVEX, VVVV, EVEX_B, T_MAP4, REX_W;
189 []>, EVEX, VVVV, EVEX_B, T_MAP4;
192 []>, EVEX, VVVV, EVEX_B, T_MAP4, REX_W;
1236 defm BLSR32 : Bls<"blsr", MRM1r, MRM1m, Xi32, "_EVEX">, EVEX;
1237 defm BLSR64 : Bls<"blsr", MRM1r, MRM1m, Xi64, "_EVEX">, EVEX;
1238 defm BLSMSK32 : Bls<"blsmsk", MRM2r, MRM2m, Xi32, "_EVEX">, EVEX;
1240 defm BLSI32 : Bls<"blsi", MRM3r, MRM3m, Xi32, "_EVEX">, EVEX;
1241 defm BLSI64 : Bls<"blsi", MRM3r, MRM3m, Xi64, "_EVEX">, EVEX;
1690 EVEX, VVVV, NoCD8, T8, PD, Sched<[WriteXCHG]>;
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H A DX86InstrArithmetic.td1337 defm ANDN32 : AndN<Xi32, "_EVEX">, EVEX, Requires<[HasBMI, HasEGPR, In64BitMode]>;
1382 EVEX, VVVV, Sched<[WriteIMulH, sched]>;
1387 EVEX, VVVV, Sched<mulx_rm_sched>;
1415 def ADCX32rr_EVEX : BinOpRRF_RF<0x66, "adcx", Xi32>, EVEX, T_MAP4, PD;
1416 def ADCX64rr_EVEX : BinOpRRF_RF<0x66, "adcx", Xi64>, EVEX, T_MAP4, PD;
1417 def ADOX32rr_EVEX : BinOpRRF_RF<0x66, "adox", Xi32>, EVEX, T_MAP4, XS;
1418 def ADOX64rr_EVEX : BinOpRRF_RF<0x66, "adox", Xi64>, EVEX, T_MAP4, XS;
1431 def ADCX32rm_EVEX : BinOpRMF_RF<0x66, "adcx", Xi32>, EVEX, T_MAP4, PD;
1432 def ADCX64rm_EVEX : BinOpRMF_RF<0x66, "adcx", Xi64>, EVEX, T_MAP4, PD;
1433 def ADOX32rm_EVEX : BinOpRMF_RF<0x66, "adox", Xi32>, EVEX, T_MAP4, XS;
[all …]
H A DX86InstrFMA3Info.cpp150 ((TSFlags & X86II::EncodingMask) == X86II::EVEX && in getFMA3Group()
H A DX86InstrSystem.td541 [(int_x86_wrssd GR32:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4;
544 [(int_x86_wrssq GR64:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4;
547 [(int_x86_wrussd GR32:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4, PD;
550 [(int_x86_wrussq GR64:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4, PD;
702 EVEX, NoCD8, T_MAP4, XS, Requires<[In64BitMode]>;
H A DX86InstrShiftRotate.td559 def ri_EVEX : RorXri<t>, EVEX;
560 def mi_EVEX : RorXmi<t>, EVEX;
590 def rr_EVEX : ShiftXrr<m, t>, EVEX;
591 def rm_EVEX : ShiftXrm<m, t>, EVEX;
H A DX86ReplaceableInstrs.def405 // Special table for changing EVEX logic instructions to VEX.
406 // TODO: Should we run EVEX->VEX earlier?
H A DX86RegisterInfo.td95 // APX only, requires REX2 or EVEX.
211 // APX only, requires REX2 or EVEX.
258 // APX only, requires REX2 or EVEX.
300 // APX only, requires REX2 or EVEX.
H A DX86FixupVectorConstants.cpp378 if ((MI.getDesc().TSFlags & X86II::EncodingMask) == X86II::EVEX) in processInstruction()
H A DX86InstrAMX.td50 defm "" : AMX_TILE_COMMON<"_EVEX", HasEGPR>, EVEX, NoCD8;
H A DX86InstrFormats.td195 // Force the instruction to use REX2/VEX/EVEX encoding.
H A DX86InstrUtils.td44 class EVEX { Encoding OpEnc = EncEVEX; }
119 class NF: T_MAP4, EVEX, EVEX_NF;
121 class PL: T_MAP4, EVEX, ExplicitEVEXPrefix;
835 EVEX, VVVV, Requires<[HasAVX512]>;
H A DX86InstrSSE.td6777 EVEX, NoCD8, T_MAP4, Sched<[SchedWriteVecIMul.XMM]>;
6785 EVEX, NoCD8, T_MAP4,
6791 EVEX, NoCD8, T_MAP4;
6794 EVEX, NoCD8, T_MAP4;
6797 EVEX, NoCD8, T_MAP4;
6802 EVEX, NoCD8, T_MAP4;
6806 EVEX, NoCD8, T_MAP4;
6809 EVEX, NoCD8, T_MAP4;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp39 enum PrefixKind { None, REX, REX2, XOP, VEX2, VEX3, EVEX }; enumerator
172 assert((!R2 || (Kind <= REX2 || Kind == EVEX)) && "invalid setting"); in setR2()
176 assert((Kind <= REX2 || Kind == EVEX) && "invalid setting"); in setX2()
181 assert((Kind <= REX2 || Kind == EVEX) && "invalid setting"); in setB2()
277 case EVEX: in determineOptimalKind()
312 case EVEX: in emit()
407 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX; in isDispOrCDisp8()
985 case X86II::EVEX: in emitVEXOpcodePrefix()
986 Prefix.setLowerBound(EVEX); in emitVEXOpcodePrefix()
H A DX86BaseInfo.h831 EVEX = 3 << EncodingShift, enumerator
1260 if (Encoding == X86II::EVEX) in canUseApxExtendedReg()
H A DX86MCTargetDesc.cpp543 bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX; in clearsSuperRegisters()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DX86CompressEVEXTablesEmitter.cpp186 else if (RI.Encoding == X86Local::EVEX && !RI.HasEVEX_K && !RI.HasEVEX_L2 && in run()
H A DX86RecognizableInstr.h172 enum { VEX = 1, XOP = 2, EVEX = 3 }; enumerator
H A DX86ManualCompressEVEXTables.def9 // This file defines all the entries in X86 EVEX compression tables that need
H A DX86RecognizableInstr.cpp195 if (Encoding == X86Local::EVEX) { in insnContext()
/freebsd/sys/contrib/openzfs/module/
H A DKbuild.in499 # aware of x86 EVEX prefix instructions used for AVX512.
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp3762 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX; in validateInstruction()
4008 (MCID.TSFlags & X86II::EncodingMask) != X86II::EVEX) in checkTargetMatchPredicate()

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