/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrAVX512.td | 663 EVEX, VVVV, EVEX_CD8<32, CD8VT1>, 828 // smaller extract to enable EVEX->VEX. 861 // smaller extract to enable EVEX->VEX. 2655 EVEX, TB, PD; 2664 EVEX, TB; 2678 EVEX, TB, PD, REX_W; 2680 EVEX, TB, XD; 2682 EVEX, TB, REX_W; 2684 EVEX, TB, XD, REX_W; 9611 EVEX, Sched<[sched]>; [all …]
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H A D | X86InstrPredicates.td | 12 // EVEX. Not all X86 instructions are extended for EGPR. The following is an 19 // * EVEX space 20 // All instructions in the EVEX space can access the EGPR in their 24 // the REX2/EVEX prefix when EGPR is used, i.e. the opcode and opcode name are 29 // promoted into EVEX space. Encoding space changes after the promotion, opcode
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H A D | X86CompressEVEX.cpp | 211 if ((TSFlags & X86II::EncodingMask) != X86II::EVEX) in CompressEVEXImpl() 258 case X86II::EVEX: in CompressEVEXImpl()
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H A D | X86InstrVMX.td | 27 EVEX, NoCD8, T_MAP4, XS, Requires<[In64BitMode]>; 38 EVEX, NoCD8, T_MAP4, XS, Requires<[In64BitMode]>;
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H A D | X86InstrMisc.td | 168 []>, EVEX, VVVV, EVEX_B, T_MAP4; 171 []>, EVEX, VVVV, EVEX_B, T_MAP4, REX_W; 189 []>, EVEX, VVVV, EVEX_B, T_MAP4; 192 []>, EVEX, VVVV, EVEX_B, T_MAP4, REX_W; 1236 defm BLSR32 : Bls<"blsr", MRM1r, MRM1m, Xi32, "_EVEX">, EVEX; 1237 defm BLSR64 : Bls<"blsr", MRM1r, MRM1m, Xi64, "_EVEX">, EVEX; 1238 defm BLSMSK32 : Bls<"blsmsk", MRM2r, MRM2m, Xi32, "_EVEX">, EVEX; 1240 defm BLSI32 : Bls<"blsi", MRM3r, MRM3m, Xi32, "_EVEX">, EVEX; 1241 defm BLSI64 : Bls<"blsi", MRM3r, MRM3m, Xi64, "_EVEX">, EVEX; 1690 EVEX, VVVV, NoCD8, T8, PD, Sched<[WriteXCHG]>; [all …]
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H A D | X86InstrArithmetic.td | 1337 defm ANDN32 : AndN<Xi32, "_EVEX">, EVEX, Requires<[HasBMI, HasEGPR, In64BitMode]>; 1382 EVEX, VVVV, Sched<[WriteIMulH, sched]>; 1387 EVEX, VVVV, Sched<mulx_rm_sched>; 1415 def ADCX32rr_EVEX : BinOpRRF_RF<0x66, "adcx", Xi32>, EVEX, T_MAP4, PD; 1416 def ADCX64rr_EVEX : BinOpRRF_RF<0x66, "adcx", Xi64>, EVEX, T_MAP4, PD; 1417 def ADOX32rr_EVEX : BinOpRRF_RF<0x66, "adox", Xi32>, EVEX, T_MAP4, XS; 1418 def ADOX64rr_EVEX : BinOpRRF_RF<0x66, "adox", Xi64>, EVEX, T_MAP4, XS; 1431 def ADCX32rm_EVEX : BinOpRMF_RF<0x66, "adcx", Xi32>, EVEX, T_MAP4, PD; 1432 def ADCX64rm_EVEX : BinOpRMF_RF<0x66, "adcx", Xi64>, EVEX, T_MAP4, PD; 1433 def ADOX32rm_EVEX : BinOpRMF_RF<0x66, "adox", Xi32>, EVEX, T_MAP4, XS; [all …]
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H A D | X86InstrFMA3Info.cpp | 150 ((TSFlags & X86II::EncodingMask) == X86II::EVEX && in getFMA3Group()
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H A D | X86InstrSystem.td | 541 [(int_x86_wrssd GR32:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4; 544 [(int_x86_wrssq GR64:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4; 547 [(int_x86_wrussd GR32:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4, PD; 550 [(int_x86_wrussq GR64:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4, PD; 702 EVEX, NoCD8, T_MAP4, XS, Requires<[In64BitMode]>;
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H A D | X86InstrShiftRotate.td | 559 def ri_EVEX : RorXri<t>, EVEX; 560 def mi_EVEX : RorXmi<t>, EVEX; 590 def rr_EVEX : ShiftXrr<m, t>, EVEX; 591 def rm_EVEX : ShiftXrm<m, t>, EVEX;
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H A D | X86ReplaceableInstrs.def | 405 // Special table for changing EVEX logic instructions to VEX. 406 // TODO: Should we run EVEX->VEX earlier?
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H A D | X86RegisterInfo.td | 95 // APX only, requires REX2 or EVEX. 211 // APX only, requires REX2 or EVEX. 258 // APX only, requires REX2 or EVEX. 300 // APX only, requires REX2 or EVEX.
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H A D | X86FixupVectorConstants.cpp | 378 if ((MI.getDesc().TSFlags & X86II::EncodingMask) == X86II::EVEX) in processInstruction()
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H A D | X86InstrAMX.td | 50 defm "" : AMX_TILE_COMMON<"_EVEX", HasEGPR>, EVEX, NoCD8;
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H A D | X86InstrFormats.td | 195 // Force the instruction to use REX2/VEX/EVEX encoding.
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H A D | X86InstrUtils.td | 44 class EVEX { Encoding OpEnc = EncEVEX; } 119 class NF: T_MAP4, EVEX, EVEX_NF; 121 class PL: T_MAP4, EVEX, ExplicitEVEXPrefix; 835 EVEX, VVVV, Requires<[HasAVX512]>;
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H A D | X86InstrSSE.td | 6777 EVEX, NoCD8, T_MAP4, Sched<[SchedWriteVecIMul.XMM]>; 6785 EVEX, NoCD8, T_MAP4, 6791 EVEX, NoCD8, T_MAP4; 6794 EVEX, NoCD8, T_MAP4; 6797 EVEX, NoCD8, T_MAP4; 6802 EVEX, NoCD8, T_MAP4; 6806 EVEX, NoCD8, T_MAP4; 6809 EVEX, NoCD8, T_MAP4;
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 39 enum PrefixKind { None, REX, REX2, XOP, VEX2, VEX3, EVEX }; enumerator 172 assert((!R2 || (Kind <= REX2 || Kind == EVEX)) && "invalid setting"); in setR2() 176 assert((Kind <= REX2 || Kind == EVEX) && "invalid setting"); in setX2() 181 assert((Kind <= REX2 || Kind == EVEX) && "invalid setting"); in setB2() 277 case EVEX: in determineOptimalKind() 312 case EVEX: in emit() 407 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX; in isDispOrCDisp8() 985 case X86II::EVEX: in emitVEXOpcodePrefix() 986 Prefix.setLowerBound(EVEX); in emitVEXOpcodePrefix()
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H A D | X86BaseInfo.h | 831 EVEX = 3 << EncodingShift, enumerator 1260 if (Encoding == X86II::EVEX) in canUseApxExtendedReg()
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H A D | X86MCTargetDesc.cpp | 543 bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX; in clearsSuperRegisters()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | X86CompressEVEXTablesEmitter.cpp | 186 else if (RI.Encoding == X86Local::EVEX && !RI.HasEVEX_K && !RI.HasEVEX_L2 && in run()
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H A D | X86RecognizableInstr.h | 172 enum { VEX = 1, XOP = 2, EVEX = 3 }; enumerator
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H A D | X86ManualCompressEVEXTables.def | 9 // This file defines all the entries in X86 EVEX compression tables that need
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H A D | X86RecognizableInstr.cpp | 195 if (Encoding == X86Local::EVEX) { in insnContext()
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/freebsd/sys/contrib/openzfs/module/ |
H A D | Kbuild.in | 499 # aware of x86 EVEX prefix instructions used for AVX512.
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 3762 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX; in validateInstruction() 4008 (MCID.TSFlags & X86II::EncodingMask) != X86II::EVEX) in checkTargetMatchPredicate()
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