/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 710 FSHL, enumerator
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 3377 { ISD::FSHL, MVT::v8i64, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost() 3378 { ISD::FSHL, MVT::v4i64, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost() 3379 { ISD::FSHL, MVT::v2i64, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost() 3380 { ISD::FSHL, MVT::v16i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost() 3381 { ISD::FSHL, MVT::v8i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost() 3382 { ISD::FSHL, MVT::v4i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost() 3383 { ISD::FSHL, MVT::v32i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost() 3384 { ISD::FSHL, MVT::v16i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost() 3969 { ISD::FSHL, MVT::i64, { 4, 4, 1, 4 } }, in getIntrinsicInstrCost() 4063 ISD = ISD::FSHL; in getIntrinsicInstrCost() [all …]
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H A D | X86ISelLowering.h | 39 FSHL, enumerator
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H A D | X86InstrFragments.td | 132 def X86fshl : SDNode<"X86ISD::FSHL", SDTIntShiftDOp>;
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H A D | X86ISelLowering.cpp | 207 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering() 1232 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering() 1438 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering() 1895 setOperationAction(ISD::FSHL, MVT::v64i8, Custom); in X86TargetLowering() 1897 setOperationAction(ISD::FSHL, MVT::v32i16, Custom); in X86TargetLowering() 1899 setOperationAction(ISD::FSHL, MVT::v16i32, Custom); in X86TargetLowering() 1969 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering() 1981 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering() 29864 unsigned FunnelOpc = IsROTL ? ISD::FSHL : ISD::FSHR; in LowerRotate() 31884 case ISD::FSHL: in LowerOperation() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 239 setOperationAction(ISD::FSHL, T, Custom); in initializeHVXLowering() 315 setOperationAction(ISD::FSHL, T, Custom); in initializeHVXLowering() 2075 assert(Opc == ISD::FSHL || Opc == ISD::FSHR); in LowerHvxFunnelShift() 2088 bool IsLeft = Opc == ISD::FSHL; in LowerHvxFunnelShift() 2122 unsigned MOpc = Opc == ISD::FSHL ? HexagonISD::MFSHL : HexagonISD::MFSHR; in LowerHvxFunnelShift() 3179 case ISD::FSHL: in LowerHvxOperation() 3219 case ISD::FSHL: in LowerHvxOperation()
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H A D | HexagonISelLowering.cpp | 1574 setOperationAction(ISD::FSHL, MVT::i32, Legal); in HexagonTargetLowering() 1575 setOperationAction(ISD::FSHL, MVT::i64, Legal); in HexagonTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 263 case ISD::FSHL: return "fshl"; in getOperationName()
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H A D | LegalizeVectorOps.cpp | 362 case ISD::FSHL: in LegalizeOp() 1018 case ISD::FSHL: in Expand()
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H A D | LegalizeIntegerTypes.cpp | 289 case ISD::FSHL: in PromoteIntegerResult() 1832 case ISD::FSHL: in PromoteIntegerOperand() 2768 case ISD::FSHL: in ExpandIntegerResult() 5021 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR; in ExpandIntRes_Rotate() 5047 Opc == ISD::FSHL ? ISD::SETNE : ISD::SETEQ); in ExpandIntRes_FunnelShift()
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H A D | TargetLowering.cpp | 2100 case ISD::FSHL: in SimplifyDemandedBits() 2105 bool IsFSHL = (Op.getOpcode() == ISD::FSHL); in SimplifyDemandedBits() 4346 (N0.getOpcode() != ISD::FSHL && N0.getOpcode() != ISD::FSHR)) in foldSetCCWithFunnelShift() 7851 bool IsFSHL = Node->getOpcode() == ISD::FSHL; in expandFunnelShift() 7857 unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL; in expandFunnelShift() 8005 Tmp2 = DAG.getNode(ISD::FSHL, dl, VT, ShOpHi, ShOpLo, ShAmt); in expandShiftParts()
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H A D | DAGCombiner.cpp | 1976 case ISD::FSHL: in visit() 5850 if ((HandOpcode == ISD::FSHL || HandOpcode == ISD::FSHR) && in hoistLogicOpWithSameOpcodeHands() 7819 if (N0.getOpcode() == ISD::FSHL && N1.getOpcode() == ISD::SHL && in visitORCommutative() 8350 if (PosOpcode == ISD::FSHL && isPowerOf2_32(EltBits)) { in MatchFunnelPosNeg() 8363 TLI.isOperationLegalOrCustom(ISD::FSHL, VT)) { in MatchFunnelPosNeg() 8364 return DAG.getNode(ISD::FSHL, DL, VT, N0, N1.getOperand(0), Pos); in MatchFunnelPosNeg() 8402 bool HasFSHL = hasOperation(ISD::FSHL, VT); in MatchRotate() 8570 Res = DAG.getNode(UseFSHL ? ISD::FSHL : ISD::FSHR, DL, VT, LHSShiftArg, in MatchRotate() 8618 LExtOp0, RExtOp0, HasFSHL, ISD::FSHL, ISD::FSHR, DL); in MatchRotate() 8624 RExtOp0, LExtOp0, HasFSHR, ISD::FSHR, ISD::FSHL, DL); in MatchRotate() [all …]
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H A D | LegalizeVectorTypes.cpp | 168 case ISD::FSHL: in ScalarizeVectorResult() 1178 case ISD::FSHL: in SplitVectorResult() 4325 case ISD::FSHL: in WidenVectorResult()
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H A D | SelectionDAG.cpp | 3468 case ISD::FSHL: in computeKnownBits() 3476 Known = computeKnownBits(Op.getOperand(Opcode == ISD::FSHL ? 0 : 1), in computeKnownBits() 3485 if (Opcode == ISD::FSHL) { in computeKnownBits() 5022 case ISD::FSHL: in canCreateUndefOrPoison()
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H A D | LegalizeDAG.cpp | 1283 case ISD::FSHL: in LegalizeOp() 3805 case ISD::FSHL: in ExpandNode()
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H A D | SelectionDAGBuilder.cpp | 6828 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR; in visitIntrinsicCall()
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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
H A D | VPIntrinsics.def | 288 VP_PROPERTY_FUNCTIONAL_SDOPC(FSHL)
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 837 ISD::FSHL, ISD::FSHR, in initActions()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 752 setOperationAction(ISD::FSHL, MVT::i64, Custom); in PPCTargetLowering() 755 setOperationAction(ISD::FSHL, MVT::i32, Custom); in PPCTargetLowering() 9067 bool IsFSHL = Op.getOpcode() == ISD::FSHL; in LowerFunnelShift() 11656 case ISD::FSHL: return LowerFunnelShift(Op, DAG); in LowerOperation() 11783 case ISD::FSHL: in ReplaceNodeResults()
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/freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
H A D | TargetSelectionDAG.td | 412 def fshl : SDNode<"ISD::FSHL" , SDTIntShiftDOp>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 521 ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FSHL, ISD::FSHR, in NVPTXTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 569 setOperationAction(ISD::FSHL, MVT::i32, Custom); in AArch64TargetLowering() 570 setOperationAction(ISD::FSHL, MVT::i64, Custom); in AArch64TargetLowering() 6050 if (Op.getOpcode() == ISD::FSHL) { in LowerFunnelShift() 6424 case ISD::FSHL: in LowerOperation()
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