1//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target-independent interfaces used by SelectionDAG 10// instruction selection generators. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Selection DAG Type Constraint definitions. 16// 17// Note that the semantics of these constraints are hard coded into tblgen. To 18// modify or add constraints, you have to hack tblgen. 19// 20 21class SDTypeConstraint<int opnum> { 22 int OperandNum = opnum; 23} 24 25// SDTCisVT - The specified operand has exactly this VT. 26class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 27 ValueType VT = vt; 28} 29 30class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 31 32// SDTCisInt - The specified operand has integer type. 33class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 34 35// SDTCisFP - The specified operand has floating-point type. 36class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 37 38// SDTCisVec - The specified operand has a vector type. 39class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 40 41// SDTCisSameAs - The two specified operands have identical types. 42class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 43 int OtherOperandNum = OtherOp; 44} 45 46// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 47// smaller than the 'Other' operand. 48class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 49 int OtherOperandNum = OtherOp; 50} 51 52class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 53 int BigOperandNum = BigOp; 54} 55 56/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 57/// type as the element type of OtherOp, which is a vector type. 58class SDTCisEltOfVec<int ThisOp, int OtherOp> 59 : SDTypeConstraint<ThisOp> { 60 int OtherOpNum = OtherOp; 61} 62 63/// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type 64/// with length less that of OtherOp, which is a vector type. 65class SDTCisSubVecOfVec<int ThisOp, int OtherOp> 66 : SDTypeConstraint<ThisOp> { 67 int OtherOpNum = OtherOp; 68} 69 70// SDTCVecEltisVT - The specified operand is vector type with element type 71// of VT. 72class SDTCVecEltisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 73 ValueType VT = vt; 74} 75 76// SDTCisSameNumEltsAs - The two specified operands have identical number 77// of elements. 78class SDTCisSameNumEltsAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 79 int OtherOperandNum = OtherOp; 80} 81 82// SDTCisSameSizeAs - The two specified operands have identical size. 83class SDTCisSameSizeAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 84 int OtherOperandNum = OtherOp; 85} 86 87//===----------------------------------------------------------------------===// 88// Selection DAG Type Profile definitions. 89// 90// These use the constraints defined above to describe the type requirements of 91// the various nodes. These are not hard coded into tblgen, allowing targets to 92// add their own if needed. 93// 94 95// SDTypeProfile - This profile describes the type requirements of a Selection 96// DAG node. 97class SDTypeProfile<int numresults, int numoperands, 98 list<SDTypeConstraint> constraints> { 99 int NumResults = numresults; 100 int NumOperands = numoperands; 101 list<SDTypeConstraint> Constraints = constraints; 102} 103 104// Builtin profiles. 105def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 106def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 107def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 108def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 109def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 110def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 111 112def SDTPtrAddOp : SDTypeProfile<1, 2, [ // ptradd 113 SDTCisSameAs<0, 1>, SDTCisInt<2>, SDTCisPtrTy<1> 114]>; 115def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 116 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 117]>; 118def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 119 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 120]>; 121def SDTIntShiftDOp: SDTypeProfile<1, 3, [ // fshl, fshr 122 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3> 123]>; 124def SDTIntSatNoShOp : SDTypeProfile<1, 2, [ // ssat with no shift 125 SDTCisSameAs<0, 1>, SDTCisInt<2> 126]>; 127def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem 128 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0> 129]>; 130def SDTIntScaledBinOp : SDTypeProfile<1, 3, [ // smulfix, sdivfix, etc 131 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3> 132]>; 133 134def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 135 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 136]>; 137def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 138 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 139]>; 140def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 141 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 142]>; 143def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // bitreverse 144 SDTCisSameAs<0, 1>, SDTCisInt<0> 145]>; 146def SDTIntBitCountUnaryOp : SDTypeProfile<1, 1, [ // ctlz, cttz 147 SDTCisInt<0>, SDTCisInt<1> 148]>; 149def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 150 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1> 151]>; 152def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 153 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1> 154]>; 155def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 156 SDTCisSameAs<0, 1>, SDTCisFP<0> 157]>; 158def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fpround 159 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1> 160]>; 161def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fpextend 162 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1> 163]>; 164def SDIsFPClassOp : SDTypeProfile<1, 2, [ // is_fpclass 165 SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>, SDTCisSameNumEltsAs<0, 1> 166]>; 167def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 168 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1> 169]>; 170def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 171 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1> 172]>; 173def SDTFPToIntSatOp : SDTypeProfile<1, 2, [ // fp_to_[su]int_sat 174 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>, SDTCisVT<2, OtherVT> 175]>; 176def SDTFPExpOp : SDTypeProfile<1, 2, [ // ldexp 177 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2> 178]>; 179def SDTGetFPStateOp : SDTypeProfile<1, 0, [ // get_fpenv, get_fpmode 180 SDTCisInt<0> 181]>; 182def SDTSetFPStateOp : SDTypeProfile<0, 1, [ // set_fpenv, set_fpmode 183 SDTCisInt<0> 184]>; 185def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 186 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 187 SDTCisVTSmallerThanOp<2, 1> 188]>; 189def SDTExtInvec : SDTypeProfile<1, 1, [ // sext_invec 190 SDTCisInt<0>, SDTCisVec<0>, SDTCisInt<1>, SDTCisVec<1>, 191 SDTCisOpSmallerThanOp<1, 0> 192]>; 193def SDTFreeze : SDTypeProfile<1, 1, [ 194 SDTCisSameAs<0, 1> 195]>; 196 197def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 198 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 199]>; 200 201def SDTSelect : SDTypeProfile<1, 3, [ // select 202 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 203]>; 204 205def SDTVSelect : SDTypeProfile<1, 3, [ // vselect 206 SDTCisVec<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisSameNumEltsAs<0, 1> 207]>; 208 209def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 210 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 211 SDTCisVT<5, OtherVT> 212]>; 213 214def SDTBr : SDTypeProfile<0, 1, [ // br 215 SDTCisVT<0, OtherVT> 216]>; 217 218def SDTBrCC : SDTypeProfile<0, 4, [ // brcc 219 SDTCisVT<0, OtherVT>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 220]>; 221 222def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 223 SDTCisInt<0>, SDTCisVT<1, OtherVT> 224]>; 225 226def SDTBrind : SDTypeProfile<0, 1, [ // brind 227 SDTCisPtrTy<0> 228]>; 229 230def SDTCatchret : SDTypeProfile<0, 2, [ // catchret 231 SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT> 232]>; 233 234def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 235 236def SDTUBSANTrap : SDTypeProfile<0, 1, []>; // ubsantrap 237 238def SDTLoad : SDTypeProfile<1, 1, [ // load 239 SDTCisPtrTy<1> 240]>; 241 242def SDTStore : SDTypeProfile<0, 2, [ // store 243 SDTCisPtrTy<1> 244]>; 245 246def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 247 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 248]>; 249 250def SDTMaskedStore: SDTypeProfile<0, 4, [ // masked store 251 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2>, SDTCisVec<3>, SDTCisSameNumEltsAs<0, 3> 252]>; 253 254def SDTMaskedLoad: SDTypeProfile<1, 4, [ // masked load 255 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2>, SDTCisVec<3>, SDTCisSameAs<0, 4>, 256 SDTCisSameNumEltsAs<0, 3> 257]>; 258 259def SDTMaskedGather : SDTypeProfile<1, 4, [ 260 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVec<2>, SDTCisPtrTy<3>, SDTCisVec<4>, 261 SDTCisSameNumEltsAs<0, 2>, SDTCisSameNumEltsAs<0, 4> 262]>; 263 264def SDTMaskedScatter : SDTypeProfile<0, 4, [ 265 SDTCisVec<0>, SDTCisVec<1>, SDTCisPtrTy<2>, SDTCisVec<3>, 266 SDTCisSameNumEltsAs<0, 1>, SDTCisSameNumEltsAs<0, 3> 267]>; 268 269def SDTVecShuffle : SDTypeProfile<1, 2, [ 270 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 271]>; 272def SDTVecSlice : SDTypeProfile<1, 3, [ // vector splice 273 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisInt<3> 274]>; 275def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 276 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 277]>; 278def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 279 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 280]>; 281def SDTVecReduce : SDTypeProfile<1, 1, [ // vector reduction 282 SDTCisInt<0>, SDTCisVec<1> 283]>; 284def SDTFPVecReduce : SDTypeProfile<1, 1, [ // FP vector reduction 285 SDTCisFP<0>, SDTCisVec<1> 286]>; 287 288def SDTVecReverse : SDTypeProfile<1, 1, [ // vector reverse 289 SDTCisVec<0>, SDTCisSameAs<0,1> 290]>; 291 292def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract 293 SDTCisSubVecOfVec<0,1>, SDTCisInt<2> 294]>; 295def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert 296 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3> 297]>; 298 299def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch 300 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1> 301]>; 302 303def SDTAtomicFence : SDTypeProfile<0, 2, [ 304 SDTCisSameAs<0,1>, SDTCisPtrTy<0> 305]>; 306def SDTAtomic3 : SDTypeProfile<1, 3, [ 307 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 308]>; 309def SDTAtomic2 : SDTypeProfile<1, 2, [ 310 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 311]>; 312 313def SDTFPAtomic2 : SDTypeProfile<1, 2, [ 314 SDTCisSameAs<0,2>, SDTCisFP<0>, SDTCisPtrTy<1> 315]>; 316 317def SDTAtomicStore : SDTypeProfile<0, 2, [ 318 SDTCisInt<0>, SDTCisPtrTy<1> 319]>; 320def SDTAtomicLoad : SDTypeProfile<1, 1, [ 321 SDTCisInt<0>, SDTCisPtrTy<1> 322]>; 323 324class SDCallSeqStart<list<SDTypeConstraint> constraints> : 325 SDTypeProfile<0, 2, constraints>; 326class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 327 SDTypeProfile<0, 2, constraints>; 328 329//===----------------------------------------------------------------------===// 330// Selection DAG Node definitions. 331// 332class SDNode<string opcode, SDTypeProfile typeprof, 333 list<SDNodeProperty> props = [], string sdclass = "SDNode"> 334 : SDPatternOperator { 335 string Opcode = opcode; 336 string SDClass = sdclass; 337 let Properties = props; 338 SDTypeProfile TypeProfile = typeprof; 339} 340 341// Special TableGen-recognized dag nodes 342def set; 343def implicit; 344def node; 345def srcvalue; 346 347def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 348def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 349def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 350def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 351def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 352def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 353def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 354def vscale : SDNode<"ISD::VSCALE" , SDTIntUnaryOp, []>; 355def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 356 "GlobalAddressSDNode">; 357def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 358 "GlobalAddressSDNode">; 359def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 360 "GlobalAddressSDNode">; 361def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 362 "GlobalAddressSDNode">; 363def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 364 "ConstantPoolSDNode">; 365def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 366 "ConstantPoolSDNode">; 367def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 368 "JumpTableSDNode">; 369def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 370 "JumpTableSDNode">; 371def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 372 "FrameIndexSDNode">; 373def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 374 "FrameIndexSDNode">; 375def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 376 "ExternalSymbolSDNode">; 377def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 378 "ExternalSymbolSDNode">; 379def mcsym: SDNode<"ISD::MCSymbol", SDTPtrLeaf, [], "MCSymbolSDNode">; 380def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 381 "BlockAddressSDNode">; 382def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 383 "BlockAddressSDNode">; 384 385def add : SDNode<"ISD::ADD" , SDTIntBinOp , 386 [SDNPCommutative, SDNPAssociative]>; 387def ptradd : SDNode<"ISD::ADD" , SDTPtrAddOp, []>; 388def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 389def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 390 [SDNPCommutative, SDNPAssociative]>; 391def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 392def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 393def avgfloors : SDNode<"ISD::AVGFLOORS" , SDTIntBinOp, [SDNPCommutative]>; 394def avgflooru : SDNode<"ISD::AVGFLOORU" , SDTIntBinOp, [SDNPCommutative]>; 395def avgceils : SDNode<"ISD::AVGCEILS" , SDTIntBinOp, [SDNPCommutative]>; 396def avgceilu : SDNode<"ISD::AVGCEILU" , SDTIntBinOp, [SDNPCommutative]>; 397def abds : SDNode<"ISD::ABDS" , SDTIntBinOp, [SDNPCommutative]>; 398def abdu : SDNode<"ISD::ABDU" , SDTIntBinOp, [SDNPCommutative]>; 399def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 400def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 401def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 402def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 403def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 404def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 405def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>; 406def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>; 407def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 408def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 409def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 410def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 411def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 412def fshl : SDNode<"ISD::FSHL" , SDTIntShiftDOp>; 413def fshr : SDNode<"ISD::FSHR" , SDTIntShiftDOp>; 414def and : SDNode<"ISD::AND" , SDTIntBinOp, 415 [SDNPCommutative, SDNPAssociative]>; 416def or : SDNode<"ISD::OR" , SDTIntBinOp, 417 [SDNPCommutative, SDNPAssociative]>; 418def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 419 [SDNPCommutative, SDNPAssociative]>; 420def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 421 [SDNPCommutative, SDNPOutGlue]>; 422def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 423 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>; 424def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 425 [SDNPOutGlue]>; 426def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 427 [SDNPOutGlue, SDNPInGlue]>; 428def smin : SDNode<"ISD::SMIN" , SDTIntBinOp, 429 [SDNPCommutative, SDNPAssociative]>; 430def smax : SDNode<"ISD::SMAX" , SDTIntBinOp, 431 [SDNPCommutative, SDNPAssociative]>; 432def umin : SDNode<"ISD::UMIN" , SDTIntBinOp, 433 [SDNPCommutative, SDNPAssociative]>; 434def umax : SDNode<"ISD::UMAX" , SDTIntBinOp, 435 [SDNPCommutative, SDNPAssociative]>; 436 437def saddsat : SDNode<"ISD::SADDSAT" , SDTIntBinOp, [SDNPCommutative]>; 438def uaddsat : SDNode<"ISD::UADDSAT" , SDTIntBinOp, [SDNPCommutative]>; 439def ssubsat : SDNode<"ISD::SSUBSAT" , SDTIntBinOp>; 440def usubsat : SDNode<"ISD::USUBSAT" , SDTIntBinOp>; 441def sshlsat : SDNode<"ISD::SSHLSAT" , SDTIntBinOp>; 442def ushlsat : SDNode<"ISD::USHLSAT" , SDTIntBinOp>; 443 444def smulfix : SDNode<"ISD::SMULFIX" , SDTIntScaledBinOp, [SDNPCommutative]>; 445def smulfixsat : SDNode<"ISD::SMULFIXSAT", SDTIntScaledBinOp, [SDNPCommutative]>; 446def umulfix : SDNode<"ISD::UMULFIX" , SDTIntScaledBinOp, [SDNPCommutative]>; 447def umulfixsat : SDNode<"ISD::UMULFIXSAT", SDTIntScaledBinOp, [SDNPCommutative]>; 448def sdivfix : SDNode<"ISD::SDIVFIX" , SDTIntScaledBinOp>; 449def sdivfixsat : SDNode<"ISD::SDIVFIXSAT", SDTIntScaledBinOp>; 450def udivfix : SDNode<"ISD::UDIVFIX" , SDTIntScaledBinOp>; 451def udivfixsat : SDNode<"ISD::UDIVFIXSAT", SDTIntScaledBinOp>; 452 453def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 454def sext_invec : SDNode<"ISD::SIGN_EXTEND_VECTOR_INREG", SDTExtInvec>; 455def zext_invec : SDNode<"ISD::ZERO_EXTEND_VECTOR_INREG", SDTExtInvec>; 456 457def abs : SDNode<"ISD::ABS" , SDTIntUnaryOp>; 458def bitreverse : SDNode<"ISD::BITREVERSE" , SDTIntUnaryOp>; 459def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 460def ctlz : SDNode<"ISD::CTLZ" , SDTIntBitCountUnaryOp>; 461def cttz : SDNode<"ISD::CTTZ" , SDTIntBitCountUnaryOp>; 462def ctpop : SDNode<"ISD::CTPOP" , SDTIntBitCountUnaryOp>; 463def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntBitCountUnaryOp>; 464def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntBitCountUnaryOp>; 465def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 466def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 467def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 468def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 469def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>; 470def addrspacecast : SDNode<"ISD::ADDRSPACECAST", SDTUnaryOp>; 471def freeze : SDNode<"ISD::FREEZE" , SDTFreeze>; 472def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 473def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 474 475def vecreduce_add : SDNode<"ISD::VECREDUCE_ADD", SDTVecReduce>; 476def vecreduce_smax : SDNode<"ISD::VECREDUCE_SMAX", SDTVecReduce>; 477def vecreduce_umax : SDNode<"ISD::VECREDUCE_UMAX", SDTVecReduce>; 478def vecreduce_smin : SDNode<"ISD::VECREDUCE_SMIN", SDTVecReduce>; 479def vecreduce_umin : SDNode<"ISD::VECREDUCE_UMIN", SDTVecReduce>; 480def vecreduce_fadd : SDNode<"ISD::VECREDUCE_FADD", SDTFPVecReduce>; 481def vecreduce_fmin : SDNode<"ISD::VECREDUCE_FMIN", SDTFPVecReduce>; 482def vecreduce_fmax : SDNode<"ISD::VECREDUCE_FMAX", SDTFPVecReduce>; 483def vecreduce_fminimum : SDNode<"ISD::VECREDUCE_FMINIMUM", SDTFPVecReduce>; 484def vecreduce_fmaximum : SDNode<"ISD::VECREDUCE_FMAXIMUM", SDTFPVecReduce>; 485 486def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 487def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 488def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 489def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 490def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 491def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp, [SDNPCommutative]>; 492def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp, [SDNPCommutative]>; 493def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 494def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp, 495 [SDNPCommutative, SDNPAssociative]>; 496def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp, 497 [SDNPCommutative, SDNPAssociative]>; 498def fminnum_ieee : SDNode<"ISD::FMINNUM_IEEE", SDTFPBinOp, 499 [SDNPCommutative]>; 500def fmaxnum_ieee : SDNode<"ISD::FMAXNUM_IEEE", SDTFPBinOp, 501 [SDNPCommutative]>; 502def fminimum : SDNode<"ISD::FMINIMUM" , SDTFPBinOp, 503 [SDNPCommutative, SDNPAssociative]>; 504def fmaximum : SDNode<"ISD::FMAXIMUM" , SDTFPBinOp, 505 [SDNPCommutative, SDNPAssociative]>; 506def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>; 507def fcanonicalize : SDNode<"ISD::FCANONICALIZE", SDTFPUnaryOp>; 508def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 509def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 510def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 511def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 512def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 513def fexp10 : SDNode<"ISD::FEXP10" , SDTFPUnaryOp>; 514def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>; 515def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 516def fldexp : SDNode<"ISD::FLDEXP" , SDTFPExpOp>; 517def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 518def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 519def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 520def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 521def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 522def fround : SDNode<"ISD::FROUND" , SDTFPUnaryOp>; 523def froundeven : SDNode<"ISD::FROUNDEVEN" , SDTFPUnaryOp>; 524 525def lround : SDNode<"ISD::LROUND" , SDTFPToIntOp>; 526def llround : SDNode<"ISD::LLROUND" , SDTFPToIntOp>; 527def lrint : SDNode<"ISD::LRINT" , SDTFPToIntOp>; 528def llrint : SDNode<"ISD::LLRINT" , SDTFPToIntOp>; 529 530def fpround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 531def fpextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 532def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 533 534def is_fpclass : SDNode<"ISD::IS_FPCLASS" , SDIsFPClassOp>; 535 536def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 537def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 538def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 539def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 540def fp_to_sint_sat : SDNode<"ISD::FP_TO_SINT_SAT" , SDTFPToIntSatOp>; 541def fp_to_uint_sat : SDNode<"ISD::FP_TO_UINT_SAT" , SDTFPToIntSatOp>; 542def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>; 543def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>; 544 545def strict_fadd : SDNode<"ISD::STRICT_FADD", 546 SDTFPBinOp, [SDNPHasChain, SDNPCommutative]>; 547def strict_fsub : SDNode<"ISD::STRICT_FSUB", 548 SDTFPBinOp, [SDNPHasChain]>; 549def strict_fmul : SDNode<"ISD::STRICT_FMUL", 550 SDTFPBinOp, [SDNPHasChain, SDNPCommutative]>; 551def strict_fdiv : SDNode<"ISD::STRICT_FDIV", 552 SDTFPBinOp, [SDNPHasChain]>; 553def strict_frem : SDNode<"ISD::STRICT_FREM", 554 SDTFPBinOp, [SDNPHasChain]>; 555def strict_fma : SDNode<"ISD::STRICT_FMA", 556 SDTFPTernaryOp, [SDNPHasChain, SDNPCommutative]>; 557def strict_fsqrt : SDNode<"ISD::STRICT_FSQRT", 558 SDTFPUnaryOp, [SDNPHasChain]>; 559def strict_fsin : SDNode<"ISD::STRICT_FSIN", 560 SDTFPUnaryOp, [SDNPHasChain]>; 561def strict_fcos : SDNode<"ISD::STRICT_FCOS", 562 SDTFPUnaryOp, [SDNPHasChain]>; 563def strict_fexp2 : SDNode<"ISD::STRICT_FEXP2", 564 SDTFPUnaryOp, [SDNPHasChain]>; 565def strict_fpow : SDNode<"ISD::STRICT_FPOW", 566 SDTFPBinOp, [SDNPHasChain]>; 567def strict_fldexp : SDNode<"ISD::STRICT_FLDEXP", 568 SDTFPExpOp, [SDNPHasChain]>; 569def strict_flog2 : SDNode<"ISD::STRICT_FLOG2", 570 SDTFPUnaryOp, [SDNPHasChain]>; 571def strict_frint : SDNode<"ISD::STRICT_FRINT", 572 SDTFPUnaryOp, [SDNPHasChain]>; 573def strict_lrint : SDNode<"ISD::STRICT_LRINT", 574 SDTFPToIntOp, [SDNPHasChain]>; 575def strict_llrint : SDNode<"ISD::STRICT_LLRINT", 576 SDTFPToIntOp, [SDNPHasChain]>; 577def strict_fnearbyint : SDNode<"ISD::STRICT_FNEARBYINT", 578 SDTFPUnaryOp, [SDNPHasChain]>; 579def strict_fceil : SDNode<"ISD::STRICT_FCEIL", 580 SDTFPUnaryOp, [SDNPHasChain]>; 581def strict_ffloor : SDNode<"ISD::STRICT_FFLOOR", 582 SDTFPUnaryOp, [SDNPHasChain]>; 583def strict_lround : SDNode<"ISD::STRICT_LROUND", 584 SDTFPToIntOp, [SDNPHasChain]>; 585def strict_llround : SDNode<"ISD::STRICT_LLROUND", 586 SDTFPToIntOp, [SDNPHasChain]>; 587def strict_fround : SDNode<"ISD::STRICT_FROUND", 588 SDTFPUnaryOp, [SDNPHasChain]>; 589def strict_froundeven : SDNode<"ISD::STRICT_FROUNDEVEN", 590 SDTFPUnaryOp, [SDNPHasChain]>; 591def strict_ftrunc : SDNode<"ISD::STRICT_FTRUNC", 592 SDTFPUnaryOp, [SDNPHasChain]>; 593def strict_fminnum : SDNode<"ISD::STRICT_FMINNUM", 594 SDTFPBinOp, [SDNPHasChain, 595 SDNPCommutative, SDNPAssociative]>; 596def strict_fmaxnum : SDNode<"ISD::STRICT_FMAXNUM", 597 SDTFPBinOp, [SDNPHasChain, 598 SDNPCommutative, SDNPAssociative]>; 599def strict_fminimum : SDNode<"ISD::STRICT_FMINIMUM", 600 SDTFPBinOp, [SDNPHasChain, 601 SDNPCommutative, SDNPAssociative]>; 602def strict_fmaximum : SDNode<"ISD::STRICT_FMAXIMUM", 603 SDTFPBinOp, [SDNPHasChain, 604 SDNPCommutative, SDNPAssociative]>; 605def strict_fpround : SDNode<"ISD::STRICT_FP_ROUND", 606 SDTFPRoundOp, [SDNPHasChain]>; 607def strict_fpextend : SDNode<"ISD::STRICT_FP_EXTEND", 608 SDTFPExtendOp, [SDNPHasChain]>; 609def strict_fp_to_sint : SDNode<"ISD::STRICT_FP_TO_SINT", 610 SDTFPToIntOp, [SDNPHasChain]>; 611def strict_fp_to_uint : SDNode<"ISD::STRICT_FP_TO_UINT", 612 SDTFPToIntOp, [SDNPHasChain]>; 613def strict_sint_to_fp : SDNode<"ISD::STRICT_SINT_TO_FP", 614 SDTIntToFPOp, [SDNPHasChain]>; 615def strict_uint_to_fp : SDNode<"ISD::STRICT_UINT_TO_FP", 616 SDTIntToFPOp, [SDNPHasChain]>; 617 618def strict_f16_to_fp : SDNode<"ISD::STRICT_FP16_TO_FP", 619 SDTIntToFPOp, [SDNPHasChain]>; 620def strict_fp_to_f16 : SDNode<"ISD::STRICT_FP_TO_FP16", 621 SDTFPToIntOp, [SDNPHasChain]>; 622 623def strict_fsetcc : SDNode<"ISD::STRICT_FSETCC", SDTSetCC, [SDNPHasChain]>; 624def strict_fsetccs : SDNode<"ISD::STRICT_FSETCCS", SDTSetCC, [SDNPHasChain]>; 625 626def get_fpenv : SDNode<"ISD::GET_FPENV", SDTGetFPStateOp, [SDNPHasChain]>; 627def set_fpenv : SDNode<"ISD::SET_FPENV", SDTSetFPStateOp, [SDNPHasChain]>; 628def reset_fpenv : SDNode<"ISD::RESET_FPENV", SDTNone, [SDNPHasChain]>; 629def get_fpmode : SDNode<"ISD::GET_FPMODE", SDTGetFPStateOp, [SDNPHasChain]>; 630def set_fpmode : SDNode<"ISD::SET_FPMODE", SDTSetFPStateOp, [SDNPHasChain]>; 631def reset_fpmode : SDNode<"ISD::RESET_FPMODE", SDTNone, [SDNPHasChain]>; 632 633def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 634def select : SDNode<"ISD::SELECT" , SDTSelect>; 635def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>; 636def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 637 638def brcc : SDNode<"ISD::BR_CC" , SDTBrCC, [SDNPHasChain]>; 639def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 640def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 641def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 642def catchret : SDNode<"ISD::CATCHRET" , SDTCatchret, 643 [SDNPHasChain, SDNPSideEffect]>; 644def cleanupret : SDNode<"ISD::CLEANUPRET" , SDTNone, [SDNPHasChain]>; 645 646def trap : SDNode<"ISD::TRAP" , SDTNone, 647 [SDNPHasChain, SDNPSideEffect]>; 648def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone, 649 [SDNPHasChain, SDNPSideEffect]>; 650def ubsantrap : SDNode<"ISD::UBSANTRAP" , SDTUBSANTrap, 651 [SDNPHasChain, SDNPSideEffect]>; 652 653def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, 654 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 655 SDNPMemOperand]>; 656 657def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf, 658 [SDNPHasChain, SDNPSideEffect]>; 659 660def membarrier : SDNode<"ISD::MEMBARRIER", SDTNone, 661 [SDNPHasChain, SDNPSideEffect]>; 662 663def jump_table_debug_info : SDNode<"ISD::JUMP_TABLE_DEBUG_INFO", SDTNone, 664 [SDNPHasChain]>; 665 666def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence, 667 [SDNPHasChain, SDNPSideEffect]>; 668 669def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, 670 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 671def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, 672 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 673def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2, 674 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 675def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2, 676 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 677def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2, 678 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 679def atomic_load_clr : SDNode<"ISD::ATOMIC_LOAD_CLR" , SDTAtomic2, 680 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 681def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2, 682 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 683def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2, 684 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 685def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2, 686 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 687def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2, 688 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 689def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2, 690 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 691def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2, 692 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 693def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, 694 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 695def atomic_load_fadd : SDNode<"ISD::ATOMIC_LOAD_FADD" , SDTFPAtomic2, 696 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 697def atomic_load_fsub : SDNode<"ISD::ATOMIC_LOAD_FSUB" , SDTFPAtomic2, 698 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 699def atomic_load_fmax : SDNode<"ISD::ATOMIC_LOAD_FMAX", SDTFPAtomic2, 700 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 701def atomic_load_fmin : SDNode<"ISD::ATOMIC_LOAD_FMIN", SDTFPAtomic2, 702 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 703def atomic_load_uinc_wrap : SDNode<"ISD::ATOMIC_LOAD_UINC_WRAP", SDTAtomic2, 704 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 705def atomic_load_udec_wrap : SDNode<"ISD::ATOMIC_LOAD_UDEC_WRAP", SDTAtomic2, 706 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 707 708def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad, 709 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 710def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore, 711 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 712 713def masked_st : SDNode<"ISD::MSTORE", SDTMaskedStore, 714 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 715def masked_ld : SDNode<"ISD::MLOAD", SDTMaskedLoad, 716 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 717 718def masked_gather : SDNode<"ISD::MGATHER", SDTMaskedGather, 719 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 720 721def masked_scatter : SDNode<"ISD::MSCATTER", SDTMaskedScatter, 722 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 723 724// Do not use ld, st directly. Use load, extload, sextload, zextload, store, 725// and truncst (see below). 726def ld : SDNode<"ISD::LOAD" , SDTLoad, 727 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 728def st : SDNode<"ISD::STORE" , SDTStore, 729 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 730def ist : SDNode<"ISD::STORE" , SDTIStore, 731 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 732 733def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 734def vector_reverse : SDNode<"ISD::VECTOR_REVERSE", SDTVecReverse>; 735def vector_splice : SDNode<"ISD::VECTOR_SPLICE", SDTVecSlice, []>; 736def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 737def splat_vector : SDNode<"ISD::SPLAT_VECTOR", SDTypeProfile<1, 1, []>, []>; 738def step_vector : SDNode<"ISD::STEP_VECTOR", SDTypeProfile<1, 1, 739 [SDTCisVec<0>, SDTCisInt<1>]>, []>; 740def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 741 []>; 742 743// vector_extract/vector_insert are deprecated. extractelt/insertelt 744// are preferred. 745def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 746 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 747def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 748 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 749def concat_vectors : SDNode<"ISD::CONCAT_VECTORS", 750 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>; 751 752// This operator does not do subvector type checking. The ARM 753// backend, at least, needs it. 754def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR", 755 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>, 756 []>; 757def vector_insert_subvec : SDNode<"ISD::INSERT_SUBVECTOR", 758 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVec<2>, SDTCisInt<3>]>, 759 []>; 760 761// This operator does subvector type checking. 762def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>; 763def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>; 764 765// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 766// these internally. Don't reference these directly. 767def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 768 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 769 [SDNPHasChain]>; 770def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 771 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 772 [SDNPHasChain]>; 773def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 774 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 775 776def SDT_assert : SDTypeProfile<1, 1, 777 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>; 778def assertsext : SDNode<"ISD::AssertSext", SDT_assert>; 779def assertzext : SDNode<"ISD::AssertZext", SDT_assert>; 780def assertalign : SDNode<"ISD::AssertAlign", SDT_assert>; 781 782//===----------------------------------------------------------------------===// 783// Selection DAG Condition Codes 784 785class CondCode<string fcmpName = "", string icmpName = ""> { 786 string ICmpPredicate = icmpName; 787 string FCmpPredicate = fcmpName; 788} 789 790// ISD::CondCode enums, and mapping to CmpInst::Predicate names 791def SETOEQ : CondCode<"FCMP_OEQ">; 792def SETOGT : CondCode<"FCMP_OGT">; 793def SETOGE : CondCode<"FCMP_OGE">; 794def SETOLT : CondCode<"FCMP_OLT">; 795def SETOLE : CondCode<"FCMP_OLE">; 796def SETONE : CondCode<"FCMP_ONE">; 797def SETO : CondCode<"FCMP_ORD">; 798def SETUO : CondCode<"FCMP_UNO">; 799def SETUEQ : CondCode<"FCMP_UEQ">; 800def SETUGT : CondCode<"FCMP_UGT", "ICMP_UGT">; 801def SETUGE : CondCode<"FCMP_UGE", "ICMP_UGE">; 802def SETULT : CondCode<"FCMP_ULT", "ICMP_ULT">; 803def SETULE : CondCode<"FCMP_ULE", "ICMP_ULE">; 804def SETUNE : CondCode<"FCMP_UNE">; 805def SETEQ : CondCode<"", "ICMP_EQ">; 806def SETGT : CondCode<"", "ICMP_SGT">; 807def SETGE : CondCode<"", "ICMP_SGE">; 808def SETLT : CondCode<"", "ICMP_SLT">; 809def SETLE : CondCode<"", "ICMP_SLE">; 810def SETNE : CondCode<"", "ICMP_NE">; 811 812//===----------------------------------------------------------------------===// 813// Selection DAG Node Transformation Functions. 814// 815// This mechanism allows targets to manipulate nodes in the output DAG once a 816// match has been formed. This is typically used to manipulate immediate 817// values. 818// 819class SDNodeXForm<SDNode opc, code xformFunction> { 820 SDNode Opcode = opc; 821 code XFormFunction = xformFunction; 822} 823 824def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 825 826//===----------------------------------------------------------------------===// 827// Selection DAG Pattern Fragments. 828// 829// Pattern fragments are reusable chunks of dags that match specific things. 830// They can take arguments and have C++ predicates that control whether they 831// match. They are intended to make the patterns for common instructions more 832// compact and readable. 833// 834 835/// PatFrags - Represents a set of pattern fragments. Each single fragment 836/// can match something on the DAG, from a single node to multiple nested other 837/// fragments. The whole set of fragments matches if any of the single 838/// fragments match. This allows e.g. matching and "add with overflow" and 839/// a regular "add" with the same fragment set. 840/// 841class PatFrags<dag ops, list<dag> frags, code pred = [{}], 842 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator { 843 dag Operands = ops; 844 list<dag> Fragments = frags; 845 code PredicateCode = pred; 846 code GISelPredicateCode = [{}]; 847 code ImmediateCode = [{}]; 848 SDNodeXForm OperandTransform = xform; 849 850 // When this is set, the PredicateCode may refer to a constant Operands 851 // vector which contains the captured nodes of the DAG, in the order listed 852 // by the Operands field above. 853 // 854 // This is useful when Fragments involves associative / commutative 855 // operators: a single piece of code can easily refer to all operands even 856 // when re-associated / commuted variants of the fragment are matched. 857 bit PredicateCodeUsesOperands = false; 858 859 // Define a few pre-packaged predicates. This helps GlobalISel import 860 // existing rules from SelectionDAG for many common cases. 861 // They will be tested prior to the code in pred and must not be used in 862 // ImmLeaf and its subclasses. 863 864 // If set to true, a predicate is added that checks for the absence of use of 865 // the first result. 866 bit HasNoUse = ?; 867 868 // Is the desired pre-packaged predicate for a load? 869 bit IsLoad = ?; 870 // Is the desired pre-packaged predicate for a store? 871 bit IsStore = ?; 872 // Is the desired pre-packaged predicate for an atomic? 873 bit IsAtomic = ?; 874 875 // cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 876 // cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 877 bit IsUnindexed = ?; 878 879 // cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD 880 bit IsNonExtLoad = ?; 881 // cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 882 bit IsAnyExtLoad = ?; 883 // cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 884 bit IsSignExtLoad = ?; 885 // cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 886 bit IsZeroExtLoad = ?; 887 // !cast<StoreSDNode>(N)->isTruncatingStore(); 888 // cast<StoreSDNode>(N)->isTruncatingStore(); 889 bit IsTruncStore = ?; 890 891 // cast<MemSDNode>(N)->getAddressSpace() == 892 // If this empty, accept any address space. 893 list<int> AddressSpaces = ?; 894 895 // cast<MemSDNode>(N)->getAlign() >= 896 // If this is empty, accept any alignment. 897 int MinAlignment = ?; 898 899 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Monotonic 900 bit IsAtomicOrderingMonotonic = ?; 901 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Acquire 902 bit IsAtomicOrderingAcquire = ?; 903 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Release 904 bit IsAtomicOrderingRelease = ?; 905 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::AcquireRelease 906 bit IsAtomicOrderingAcquireRelease = ?; 907 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::SequentiallyConsistent 908 bit IsAtomicOrderingSequentiallyConsistent = ?; 909 910 // isAcquireOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 911 // !isAcquireOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 912 bit IsAtomicOrderingAcquireOrStronger = ?; 913 914 // isReleaseOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 915 // !isReleaseOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 916 bit IsAtomicOrderingReleaseOrStronger = ?; 917 918 // cast<LoadSDNode>(N)->getMemoryVT() == MVT::<VT>; 919 // cast<StoreSDNode>(N)->getMemoryVT() == MVT::<VT>; 920 ValueType MemoryVT = ?; 921 // cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::<VT>; 922 // cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::<VT>; 923 ValueType ScalarMemoryVT = ?; 924} 925 926// Patterns and PatFrags can also subclass GISelFlags to set flags that affect 927// how GlobalISel behaves when matching them. 928class GISelFlags { 929 bit GIIgnoreCopies = ?; 930} 931 932// PatFrag - A version of PatFrags matching only a single fragment. 933class PatFrag<dag ops, dag frag, code pred = [{}], 934 SDNodeXForm xform = NOOP_SDNodeXForm> 935 : PatFrags<ops, [frag], pred, xform>; 936 937// OutPatFrag is a pattern fragment that is used as part of an output pattern 938// (not an input pattern). These do not have predicates or transforms, but are 939// used to avoid repeated subexpressions in output patterns. 940class OutPatFrag<dag ops, dag frag> 941 : PatFrag<ops, frag, [{}], NOOP_SDNodeXForm>; 942 943// PatLeaf's are pattern fragments that have no operands. This is just a helper 944// to define immediates and other common things concisely. 945class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 946 : PatFrag<(ops), frag, pred, xform>; 947 948 949// ImmLeaf is a pattern fragment with a constraint on the immediate. The 950// constraint is a function that is run on the immediate (always with the value 951// sign extended out to an int64_t) as Imm. For example: 952// 953// def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>; 954// 955// this is a more convenient form to match 'imm' nodes in than PatLeaf and also 956// is preferred over using PatLeaf because it allows the code generator to 957// reason more about the constraint. 958// 959// If FastIsel should ignore all instructions that have an operand of this type, 960// the FastIselShouldIgnore flag can be set. This is an optimization to reduce 961// the code size of the generated fast instruction selector. 962class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm, 963 SDNode ImmNode = imm> 964 : PatFrag<(ops), (vt ImmNode), [{}], xform> { 965 let ImmediateCode = pred; 966 bit FastIselShouldIgnore = false; 967 968 // Is the data type of the immediate an APInt? 969 bit IsAPInt = false; 970 971 // Is the data type of the immediate an APFloat? 972 bit IsAPFloat = false; 973} 974 975// Convenience wrapper for ImmLeaf to use timm/TargetConstant instead 976// of imm/Constant. 977class TImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm, 978 SDNode ImmNode = timm> : ImmLeaf<vt, pred, xform, ImmNode>; 979 980// An ImmLeaf except that Imm is an APInt. This is useful when you need to 981// zero-extend the immediate instead of sign-extend it. 982// 983// Note that FastISel does not currently understand IntImmLeaf and will not 984// generate code for rules that make use of it. As such, it does not make sense 985// to replace ImmLeaf with IntImmLeaf. However, replacing PatLeaf with an 986// IntImmLeaf will allow GlobalISel to import the rule. 987class IntImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 988 : ImmLeaf<vt, pred, xform> { 989 let IsAPInt = true; 990 let FastIselShouldIgnore = true; 991} 992 993// An ImmLeaf except that Imm is an APFloat. 994// 995// Note that FastISel does not currently understand FPImmLeaf and will not 996// generate code for rules that make use of it. 997class FPImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 998 : ImmLeaf<vt, pred, xform, fpimm> { 999 let IsAPFloat = true; 1000 let FastIselShouldIgnore = true; 1001} 1002 1003// Leaf fragments. 1004 1005def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 1006def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 1007 1008// Use ISD::isConstantSplatVectorAllOnes or ISD::isConstantSplatVectorAllZeros 1009// to look for the corresponding build_vector or splat_vector. Will look through 1010// bitcasts and check for either opcode, except when used as a pattern root. 1011// When used as a pattern root, only fixed-length build_vector and scalable 1012// splat_vector are supported. 1013def immAllOnesV : SDPatternOperator; // ISD::isConstantSplatVectorAllOnes 1014def immAllZerosV : SDPatternOperator; // ISD::isConstantSplatVectorAllZeros 1015 1016// Other helper fragments. 1017def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 1018def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 1019def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 1020 1021def zanyext : PatFrags<(ops node:$op), 1022 [(zext node:$op), 1023 (anyext node:$op)]>; 1024 1025// null_frag - The null pattern operator is used in multiclass instantiations 1026// which accept an SDPatternOperator for use in matching patterns for internal 1027// definitions. When expanding a pattern, if the null fragment is referenced 1028// in the expansion, the pattern is discarded and it is as-if '[]' had been 1029// specified. This allows multiclasses to have the isel patterns be optional. 1030def null_frag : SDPatternOperator; 1031 1032// load fragments. 1033def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr)> { 1034 let IsLoad = true; 1035 let IsUnindexed = true; 1036} 1037def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 1038 let IsLoad = true; 1039 let IsNonExtLoad = true; 1040} 1041 1042// extending load fragments. 1043def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 1044 let IsLoad = true; 1045 let IsAnyExtLoad = true; 1046} 1047def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 1048 let IsLoad = true; 1049 let IsSignExtLoad = true; 1050} 1051def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 1052 let IsLoad = true; 1053 let IsZeroExtLoad = true; 1054} 1055 1056def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1057 let IsLoad = true; 1058 let MemoryVT = i1; 1059} 1060def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1061 let IsLoad = true; 1062 let MemoryVT = i8; 1063} 1064def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1065 let IsLoad = true; 1066 let MemoryVT = i16; 1067} 1068def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1069 let IsLoad = true; 1070 let MemoryVT = i32; 1071} 1072def extloadi64 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1073 let IsLoad = true; 1074 let MemoryVT = i64; 1075} 1076def extloadf16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1077 let IsLoad = true; 1078 let MemoryVT = f16; 1079} 1080def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1081 let IsLoad = true; 1082 let MemoryVT = f32; 1083} 1084def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1085 let IsLoad = true; 1086 let MemoryVT = f64; 1087} 1088 1089def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1090 let IsLoad = true; 1091 let MemoryVT = i1; 1092} 1093def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1094 let IsLoad = true; 1095 let MemoryVT = i8; 1096} 1097def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1098 let IsLoad = true; 1099 let MemoryVT = i16; 1100} 1101def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1102 let IsLoad = true; 1103 let MemoryVT = i32; 1104} 1105def sextloadi64 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1106 let IsLoad = true; 1107 let MemoryVT = i64; 1108} 1109 1110def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1111 let IsLoad = true; 1112 let MemoryVT = i1; 1113} 1114def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1115 let IsLoad = true; 1116 let MemoryVT = i8; 1117} 1118def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1119 let IsLoad = true; 1120 let MemoryVT = i16; 1121} 1122def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1123 let IsLoad = true; 1124 let MemoryVT = i32; 1125} 1126def zextloadi64 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1127 let IsLoad = true; 1128 let MemoryVT = i64; 1129} 1130 1131def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1132 let IsLoad = true; 1133 let ScalarMemoryVT = i1; 1134} 1135def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1136 let IsLoad = true; 1137 let ScalarMemoryVT = i8; 1138} 1139def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1140 let IsLoad = true; 1141 let ScalarMemoryVT = i16; 1142} 1143def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1144 let IsLoad = true; 1145 let ScalarMemoryVT = i32; 1146} 1147def extloadvf16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1148 let IsLoad = true; 1149 let ScalarMemoryVT = f16; 1150} 1151def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1152 let IsLoad = true; 1153 let ScalarMemoryVT = f32; 1154} 1155def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1156 let IsLoad = true; 1157 let ScalarMemoryVT = f64; 1158} 1159 1160def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1161 let IsLoad = true; 1162 let ScalarMemoryVT = i1; 1163} 1164def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1165 let IsLoad = true; 1166 let ScalarMemoryVT = i8; 1167} 1168def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1169 let IsLoad = true; 1170 let ScalarMemoryVT = i16; 1171} 1172def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1173 let IsLoad = true; 1174 let ScalarMemoryVT = i32; 1175} 1176 1177def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1178 let IsLoad = true; 1179 let ScalarMemoryVT = i1; 1180} 1181def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1182 let IsLoad = true; 1183 let ScalarMemoryVT = i8; 1184} 1185def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1186 let IsLoad = true; 1187 let ScalarMemoryVT = i16; 1188} 1189def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1190 let IsLoad = true; 1191 let ScalarMemoryVT = i32; 1192} 1193 1194// store fragments. 1195def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 1196 (st node:$val, node:$ptr)> { 1197 let IsStore = true; 1198 let IsUnindexed = true; 1199} 1200def store : PatFrag<(ops node:$val, node:$ptr), 1201 (unindexedstore node:$val, node:$ptr)> { 1202 let IsStore = true; 1203 let IsTruncStore = false; 1204} 1205 1206// truncstore fragments. 1207def truncstore : PatFrag<(ops node:$val, node:$ptr), 1208 (unindexedstore node:$val, node:$ptr)> { 1209 let IsStore = true; 1210 let IsTruncStore = true; 1211} 1212def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 1213 (truncstore node:$val, node:$ptr)> { 1214 let IsStore = true; 1215 let MemoryVT = i8; 1216 let IsTruncStore = true; 1217} 1218def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 1219 (truncstore node:$val, node:$ptr)> { 1220 let IsStore = true; 1221 let MemoryVT = i16; 1222 let IsTruncStore = true; 1223} 1224def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 1225 (truncstore node:$val, node:$ptr)> { 1226 let IsStore = true; 1227 let MemoryVT = i32; 1228 let IsTruncStore = true; 1229} 1230def truncstorei64 : PatFrag<(ops node:$val, node:$ptr), 1231 (truncstore node:$val, node:$ptr)> { 1232 let IsStore = true; 1233 let MemoryVT = i64; 1234 let IsTruncStore = true; 1235} 1236def truncstoref16 : PatFrag<(ops node:$val, node:$ptr), 1237 (truncstore node:$val, node:$ptr)> { 1238 let IsStore = true; 1239 let MemoryVT = f16; 1240} 1241def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 1242 (truncstore node:$val, node:$ptr)> { 1243 let IsStore = true; 1244 let MemoryVT = f32; 1245} 1246def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 1247 (truncstore node:$val, node:$ptr)> { 1248 let IsStore = true; 1249 let MemoryVT = f64; 1250} 1251 1252def truncstorevi8 : PatFrag<(ops node:$val, node:$ptr), 1253 (truncstore node:$val, node:$ptr)> { 1254 let IsStore = true; 1255 let ScalarMemoryVT = i8; 1256} 1257 1258def truncstorevi16 : PatFrag<(ops node:$val, node:$ptr), 1259 (truncstore node:$val, node:$ptr)> { 1260 let IsStore = true; 1261 let ScalarMemoryVT = i16; 1262} 1263 1264def truncstorevi32 : PatFrag<(ops node:$val, node:$ptr), 1265 (truncstore node:$val, node:$ptr)> { 1266 let IsStore = true; 1267 let ScalarMemoryVT = i32; 1268} 1269 1270// indexed store fragments. 1271def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 1272 (ist node:$val, node:$base, node:$offset)> { 1273 let IsStore = true; 1274 let IsTruncStore = false; 1275} 1276 1277def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 1278 (istore node:$val, node:$base, node:$offset), [{ 1279 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1280 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 1281}]>; 1282 1283def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 1284 (ist node:$val, node:$base, node:$offset)> { 1285 let IsStore = true; 1286 let IsTruncStore = true; 1287} 1288def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 1289 (itruncstore node:$val, node:$base, node:$offset), [{ 1290 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1291 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 1292}]>; 1293def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 1294 (pre_truncst node:$val, node:$base, node:$offset)> { 1295 let IsStore = true; 1296 let MemoryVT = i1; 1297} 1298def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1299 (pre_truncst node:$val, node:$base, node:$offset)> { 1300 let IsStore = true; 1301 let MemoryVT = i8; 1302} 1303def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1304 (pre_truncst node:$val, node:$base, node:$offset)> { 1305 let IsStore = true; 1306 let MemoryVT = i16; 1307} 1308def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1309 (pre_truncst node:$val, node:$base, node:$offset)> { 1310 let IsStore = true; 1311 let MemoryVT = i32; 1312} 1313def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1314 (pre_truncst node:$val, node:$base, node:$offset)> { 1315 let IsStore = true; 1316 let MemoryVT = f32; 1317} 1318def pre_truncstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1319 (pre_truncst node:$val, node:$base, node:$offset)> { 1320 let IsStore = true; 1321 let ScalarMemoryVT = i8; 1322} 1323def pre_truncstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1324 (pre_truncst node:$val, node:$base, node:$offset)> { 1325 let IsStore = true; 1326 let ScalarMemoryVT = i16; 1327} 1328 1329def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 1330 (istore node:$val, node:$ptr, node:$offset), [{ 1331 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1332 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 1333}]>; 1334 1335def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 1336 (itruncstore node:$val, node:$base, node:$offset), [{ 1337 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1338 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 1339}]>; 1340def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 1341 (post_truncst node:$val, node:$base, node:$offset)> { 1342 let IsStore = true; 1343 let MemoryVT = i1; 1344} 1345def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1346 (post_truncst node:$val, node:$base, node:$offset)> { 1347 let IsStore = true; 1348 let MemoryVT = i8; 1349} 1350def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1351 (post_truncst node:$val, node:$base, node:$offset)> { 1352 let IsStore = true; 1353 let MemoryVT = i16; 1354} 1355def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1356 (post_truncst node:$val, node:$base, node:$offset)> { 1357 let IsStore = true; 1358 let MemoryVT = i32; 1359} 1360def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1361 (post_truncst node:$val, node:$base, node:$offset)> { 1362 let IsStore = true; 1363 let MemoryVT = f32; 1364} 1365def post_truncstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1366 (post_truncst node:$val, node:$base, node:$offset)> { 1367 let IsStore = true; 1368 let ScalarMemoryVT = i8; 1369} 1370def post_truncstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1371 (post_truncst node:$val, node:$base, node:$offset)> { 1372 let IsStore = true; 1373 let ScalarMemoryVT = i16; 1374} 1375 1376// A helper for matching undef or freeze undef 1377def undef_or_freeze_undef : PatFrags<(ops), [(undef), (freeze undef)]>; 1378 1379// TODO: Split these into volatile and unordered flavors to enable 1380// selectively legal optimizations for each. (See D66309) 1381def simple_load : PatFrag<(ops node:$ptr), 1382 (load node:$ptr), [{ 1383 return cast<LoadSDNode>(N)->isSimple(); 1384}]>; 1385def simple_store : PatFrag<(ops node:$val, node:$ptr), 1386 (store node:$val, node:$ptr), [{ 1387 return cast<StoreSDNode>(N)->isSimple(); 1388}]>; 1389 1390// nontemporal store fragments. 1391def nontemporalstore : PatFrag<(ops node:$val, node:$ptr), 1392 (store node:$val, node:$ptr), [{ 1393 return cast<StoreSDNode>(N)->isNonTemporal(); 1394}]>; 1395 1396def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 1397 (nontemporalstore node:$val, node:$ptr), [{ 1398 StoreSDNode *St = cast<StoreSDNode>(N); 1399 return St->getAlign() >= St->getMemoryVT().getStoreSize(); 1400}]>; 1401 1402def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 1403 (nontemporalstore node:$val, node:$ptr), [{ 1404 StoreSDNode *St = cast<StoreSDNode>(N); 1405 return St->getAlignment() < St->getMemoryVT().getStoreSize(); 1406}]>; 1407 1408// nontemporal load fragments. 1409def nontemporalload : PatFrag<(ops node:$ptr), 1410 (load node:$ptr), [{ 1411 return cast<LoadSDNode>(N)->isNonTemporal(); 1412}]>; 1413 1414def alignednontemporalload : PatFrag<(ops node:$ptr), 1415 (nontemporalload node:$ptr), [{ 1416 LoadSDNode *Ld = cast<LoadSDNode>(N); 1417 return Ld->getAlign() >= Ld->getMemoryVT().getStoreSize(); 1418}]>; 1419 1420// setcc convenience fragments. 1421def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 1422 (setcc node:$lhs, node:$rhs, SETOEQ)>; 1423def setogt : PatFrag<(ops node:$lhs, node:$rhs), 1424 (setcc node:$lhs, node:$rhs, SETOGT)>; 1425def setoge : PatFrag<(ops node:$lhs, node:$rhs), 1426 (setcc node:$lhs, node:$rhs, SETOGE)>; 1427def setolt : PatFrag<(ops node:$lhs, node:$rhs), 1428 (setcc node:$lhs, node:$rhs, SETOLT)>; 1429def setole : PatFrag<(ops node:$lhs, node:$rhs), 1430 (setcc node:$lhs, node:$rhs, SETOLE)>; 1431def setone : PatFrag<(ops node:$lhs, node:$rhs), 1432 (setcc node:$lhs, node:$rhs, SETONE)>; 1433def seto : PatFrag<(ops node:$lhs, node:$rhs), 1434 (setcc node:$lhs, node:$rhs, SETO)>; 1435def setuo : PatFrag<(ops node:$lhs, node:$rhs), 1436 (setcc node:$lhs, node:$rhs, SETUO)>; 1437def setueq : PatFrag<(ops node:$lhs, node:$rhs), 1438 (setcc node:$lhs, node:$rhs, SETUEQ)>; 1439def setugt : PatFrag<(ops node:$lhs, node:$rhs), 1440 (setcc node:$lhs, node:$rhs, SETUGT)>; 1441def setuge : PatFrag<(ops node:$lhs, node:$rhs), 1442 (setcc node:$lhs, node:$rhs, SETUGE)>; 1443def setult : PatFrag<(ops node:$lhs, node:$rhs), 1444 (setcc node:$lhs, node:$rhs, SETULT)>; 1445def setule : PatFrag<(ops node:$lhs, node:$rhs), 1446 (setcc node:$lhs, node:$rhs, SETULE)>; 1447def setune : PatFrag<(ops node:$lhs, node:$rhs), 1448 (setcc node:$lhs, node:$rhs, SETUNE)>; 1449def seteq : PatFrag<(ops node:$lhs, node:$rhs), 1450 (setcc node:$lhs, node:$rhs, SETEQ)>; 1451def setgt : PatFrag<(ops node:$lhs, node:$rhs), 1452 (setcc node:$lhs, node:$rhs, SETGT)>; 1453def setge : PatFrag<(ops node:$lhs, node:$rhs), 1454 (setcc node:$lhs, node:$rhs, SETGE)>; 1455def setlt : PatFrag<(ops node:$lhs, node:$rhs), 1456 (setcc node:$lhs, node:$rhs, SETLT)>; 1457def setle : PatFrag<(ops node:$lhs, node:$rhs), 1458 (setcc node:$lhs, node:$rhs, SETLE)>; 1459def setne : PatFrag<(ops node:$lhs, node:$rhs), 1460 (setcc node:$lhs, node:$rhs, SETNE)>; 1461 1462// We don't have strict FP extended loads as single DAG nodes, but we can 1463// still provide convenience fragments to match those operations. 1464def strict_extloadf32 : PatFrag<(ops node:$ptr), 1465 (strict_fpextend (f32 (load node:$ptr)))>; 1466def strict_extloadf64 : PatFrag<(ops node:$ptr), 1467 (strict_fpextend (f64 (load node:$ptr)))>; 1468 1469// Convenience fragments to match both strict and non-strict fp operations 1470def any_fadd : PatFrags<(ops node:$lhs, node:$rhs), 1471 [(strict_fadd node:$lhs, node:$rhs), 1472 (fadd node:$lhs, node:$rhs)]>; 1473def any_fsub : PatFrags<(ops node:$lhs, node:$rhs), 1474 [(strict_fsub node:$lhs, node:$rhs), 1475 (fsub node:$lhs, node:$rhs)]>; 1476def any_fmul : PatFrags<(ops node:$lhs, node:$rhs), 1477 [(strict_fmul node:$lhs, node:$rhs), 1478 (fmul node:$lhs, node:$rhs)]>; 1479def any_fdiv : PatFrags<(ops node:$lhs, node:$rhs), 1480 [(strict_fdiv node:$lhs, node:$rhs), 1481 (fdiv node:$lhs, node:$rhs)]>; 1482def any_frem : PatFrags<(ops node:$lhs, node:$rhs), 1483 [(strict_frem node:$lhs, node:$rhs), 1484 (frem node:$lhs, node:$rhs)]>; 1485def any_fma : PatFrags<(ops node:$src1, node:$src2, node:$src3), 1486 [(strict_fma node:$src1, node:$src2, node:$src3), 1487 (fma node:$src1, node:$src2, node:$src3)]>; 1488def any_fsqrt : PatFrags<(ops node:$src), 1489 [(strict_fsqrt node:$src), 1490 (fsqrt node:$src)]>; 1491def any_fsin : PatFrags<(ops node:$src), 1492 [(strict_fsin node:$src), 1493 (fsin node:$src)]>; 1494def any_fcos : PatFrags<(ops node:$src), 1495 [(strict_fcos node:$src), 1496 (fcos node:$src)]>; 1497def any_fexp2 : PatFrags<(ops node:$src), 1498 [(strict_fexp2 node:$src), 1499 (fexp2 node:$src)]>; 1500def any_fpow : PatFrags<(ops node:$lhs, node:$rhs), 1501 [(strict_fpow node:$lhs, node:$rhs), 1502 (fpow node:$lhs, node:$rhs)]>; 1503def any_fldexp : PatFrags<(ops node:$lhs, node:$rhs), 1504 [(strict_fldexp node:$lhs, node:$rhs), 1505 (fldexp node:$lhs, node:$rhs)]>; 1506def any_flog2 : PatFrags<(ops node:$src), 1507 [(strict_flog2 node:$src), 1508 (flog2 node:$src)]>; 1509def any_frint : PatFrags<(ops node:$src), 1510 [(strict_frint node:$src), 1511 (frint node:$src)]>; 1512def any_lrint : PatFrags<(ops node:$src), 1513 [(strict_lrint node:$src), 1514 (lrint node:$src)]>; 1515def any_llrint : PatFrags<(ops node:$src), 1516 [(strict_llrint node:$src), 1517 (llrint node:$src)]>; 1518def any_fnearbyint : PatFrags<(ops node:$src), 1519 [(strict_fnearbyint node:$src), 1520 (fnearbyint node:$src)]>; 1521def any_fceil : PatFrags<(ops node:$src), 1522 [(strict_fceil node:$src), 1523 (fceil node:$src)]>; 1524def any_ffloor : PatFrags<(ops node:$src), 1525 [(strict_ffloor node:$src), 1526 (ffloor node:$src)]>; 1527def any_lround : PatFrags<(ops node:$src), 1528 [(strict_lround node:$src), 1529 (lround node:$src)]>; 1530def any_llround : PatFrags<(ops node:$src), 1531 [(strict_llround node:$src), 1532 (llround node:$src)]>; 1533def any_fround : PatFrags<(ops node:$src), 1534 [(strict_fround node:$src), 1535 (fround node:$src)]>; 1536def any_froundeven : PatFrags<(ops node:$src), 1537 [(strict_froundeven node:$src), 1538 (froundeven node:$src)]>; 1539def any_ftrunc : PatFrags<(ops node:$src), 1540 [(strict_ftrunc node:$src), 1541 (ftrunc node:$src)]>; 1542def any_fmaxnum : PatFrags<(ops node:$lhs, node:$rhs), 1543 [(strict_fmaxnum node:$lhs, node:$rhs), 1544 (fmaxnum node:$lhs, node:$rhs)]>; 1545def any_fminnum : PatFrags<(ops node:$lhs, node:$rhs), 1546 [(strict_fminnum node:$lhs, node:$rhs), 1547 (fminnum node:$lhs, node:$rhs)]>; 1548def any_fmaximum : PatFrags<(ops node:$lhs, node:$rhs), 1549 [(strict_fmaximum node:$lhs, node:$rhs), 1550 (fmaximum node:$lhs, node:$rhs)]>; 1551def any_fminimum : PatFrags<(ops node:$lhs, node:$rhs), 1552 [(strict_fminimum node:$lhs, node:$rhs), 1553 (fminimum node:$lhs, node:$rhs)]>; 1554def any_fpround : PatFrags<(ops node:$src), 1555 [(strict_fpround node:$src), 1556 (fpround node:$src)]>; 1557def any_fpextend : PatFrags<(ops node:$src), 1558 [(strict_fpextend node:$src), 1559 (fpextend node:$src)]>; 1560def any_extloadf32 : PatFrags<(ops node:$ptr), 1561 [(strict_extloadf32 node:$ptr), 1562 (extloadf32 node:$ptr)]>; 1563def any_extloadf64 : PatFrags<(ops node:$ptr), 1564 [(strict_extloadf64 node:$ptr), 1565 (extloadf64 node:$ptr)]>; 1566def any_fp_to_sint : PatFrags<(ops node:$src), 1567 [(strict_fp_to_sint node:$src), 1568 (fp_to_sint node:$src)]>; 1569def any_fp_to_uint : PatFrags<(ops node:$src), 1570 [(strict_fp_to_uint node:$src), 1571 (fp_to_uint node:$src)]>; 1572def any_sint_to_fp : PatFrags<(ops node:$src), 1573 [(strict_sint_to_fp node:$src), 1574 (sint_to_fp node:$src)]>; 1575def any_uint_to_fp : PatFrags<(ops node:$src), 1576 [(strict_uint_to_fp node:$src), 1577 (uint_to_fp node:$src)]>; 1578def any_fsetcc : PatFrags<(ops node:$lhs, node:$rhs, node:$pred), 1579 [(strict_fsetcc node:$lhs, node:$rhs, node:$pred), 1580 (setcc node:$lhs, node:$rhs, node:$pred)]>; 1581def any_fsetccs : PatFrags<(ops node:$lhs, node:$rhs, node:$pred), 1582 [(strict_fsetccs node:$lhs, node:$rhs, node:$pred), 1583 (setcc node:$lhs, node:$rhs, node:$pred)]>; 1584 1585def any_f16_to_fp : PatFrags<(ops node:$src), 1586 [(f16_to_fp node:$src), 1587 (strict_f16_to_fp node:$src)]>; 1588def any_fp_to_f16 : PatFrags<(ops node:$src), 1589 [(fp_to_f16 node:$src), 1590 (strict_fp_to_f16 node:$src)]>; 1591 1592multiclass binary_atomic_op_ord { 1593 def NAME#_monotonic : PatFrag<(ops node:$ptr, node:$val), 1594 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1595 let IsAtomic = true; 1596 let IsAtomicOrderingMonotonic = true; 1597 } 1598 def NAME#_acquire : PatFrag<(ops node:$ptr, node:$val), 1599 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1600 let IsAtomic = true; 1601 let IsAtomicOrderingAcquire = true; 1602 } 1603 def NAME#_release : PatFrag<(ops node:$ptr, node:$val), 1604 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1605 let IsAtomic = true; 1606 let IsAtomicOrderingRelease = true; 1607 } 1608 def NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$val), 1609 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1610 let IsAtomic = true; 1611 let IsAtomicOrderingAcquireRelease = true; 1612 } 1613 def NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$val), 1614 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1615 let IsAtomic = true; 1616 let IsAtomicOrderingSequentiallyConsistent = true; 1617 } 1618} 1619 1620multiclass ternary_atomic_op_ord { 1621 def NAME#_monotonic : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1622 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1623 let IsAtomic = true; 1624 let IsAtomicOrderingMonotonic = true; 1625 } 1626 def NAME#_acquire : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1627 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1628 let IsAtomic = true; 1629 let IsAtomicOrderingAcquire = true; 1630 } 1631 def NAME#_release : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1632 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1633 let IsAtomic = true; 1634 let IsAtomicOrderingRelease = true; 1635 } 1636 def NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1637 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1638 let IsAtomic = true; 1639 let IsAtomicOrderingAcquireRelease = true; 1640 } 1641 def NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1642 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1643 let IsAtomic = true; 1644 let IsAtomicOrderingSequentiallyConsistent = true; 1645 } 1646} 1647 1648multiclass binary_atomic_op<SDNode atomic_op, bit IsInt = 1> { 1649 def _8 : PatFrag<(ops node:$ptr, node:$val), 1650 (atomic_op node:$ptr, node:$val)> { 1651 let IsAtomic = true; 1652 let MemoryVT = !if(IsInt, i8, ?); 1653 } 1654 def _16 : PatFrag<(ops node:$ptr, node:$val), 1655 (atomic_op node:$ptr, node:$val)> { 1656 let IsAtomic = true; 1657 let MemoryVT = !if(IsInt, i16, f16); 1658 } 1659 def _32 : PatFrag<(ops node:$ptr, node:$val), 1660 (atomic_op node:$ptr, node:$val)> { 1661 let IsAtomic = true; 1662 let MemoryVT = !if(IsInt, i32, f32); 1663 } 1664 def _64 : PatFrag<(ops node:$ptr, node:$val), 1665 (atomic_op node:$ptr, node:$val)> { 1666 let IsAtomic = true; 1667 let MemoryVT = !if(IsInt, i64, f64); 1668 } 1669 1670 defm NAME#_8 : binary_atomic_op_ord; 1671 defm NAME#_16 : binary_atomic_op_ord; 1672 defm NAME#_32 : binary_atomic_op_ord; 1673 defm NAME#_64 : binary_atomic_op_ord; 1674} 1675 1676multiclass ternary_atomic_op<SDNode atomic_op> { 1677 def _8 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1678 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1679 let IsAtomic = true; 1680 let MemoryVT = i8; 1681 } 1682 def _16 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1683 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1684 let IsAtomic = true; 1685 let MemoryVT = i16; 1686 } 1687 def _32 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1688 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1689 let IsAtomic = true; 1690 let MemoryVT = i32; 1691 } 1692 def _64 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1693 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1694 let IsAtomic = true; 1695 let MemoryVT = i64; 1696 } 1697 1698 defm NAME#_8 : ternary_atomic_op_ord; 1699 defm NAME#_16 : ternary_atomic_op_ord; 1700 defm NAME#_32 : ternary_atomic_op_ord; 1701 defm NAME#_64 : ternary_atomic_op_ord; 1702} 1703 1704defm atomic_load_add : binary_atomic_op<atomic_load_add>; 1705defm atomic_swap : binary_atomic_op<atomic_swap>; 1706defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 1707defm atomic_load_and : binary_atomic_op<atomic_load_and>; 1708defm atomic_load_clr : binary_atomic_op<atomic_load_clr>; 1709defm atomic_load_or : binary_atomic_op<atomic_load_or>; 1710defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 1711defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 1712defm atomic_load_min : binary_atomic_op<atomic_load_min>; 1713defm atomic_load_max : binary_atomic_op<atomic_load_max>; 1714defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 1715defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 1716defm atomic_cmp_swap : ternary_atomic_op<atomic_cmp_swap>; 1717 1718/// Atomic load which zeroes the excess high bits. 1719def atomic_load_zext : 1720 PatFrag<(ops node:$ptr), (atomic_load node:$ptr)> { 1721 let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic? 1722 let IsZeroExtLoad = true; 1723} 1724 1725/// Atomic load which sign extends the excess high bits. 1726def atomic_load_sext : 1727 PatFrag<(ops node:$ptr), (atomic_load node:$ptr)> { 1728 let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic? 1729 let IsSignExtLoad = true; 1730} 1731 1732def atomic_load_8 : 1733 PatFrag<(ops node:$ptr), 1734 (atomic_load node:$ptr)> { 1735 let IsAtomic = true; 1736 let MemoryVT = i8; 1737} 1738 1739def atomic_load_16 : 1740 PatFrag<(ops node:$ptr), 1741 (atomic_load node:$ptr)> { 1742 let IsAtomic = true; 1743 let MemoryVT = i16; 1744} 1745 1746def atomic_load_32 : 1747 PatFrag<(ops node:$ptr), 1748 (atomic_load node:$ptr)> { 1749 let IsAtomic = true; 1750 let MemoryVT = i32; 1751} 1752def atomic_load_64 : 1753 PatFrag<(ops node:$ptr), 1754 (atomic_load node:$ptr)> { 1755 let IsAtomic = true; 1756 let MemoryVT = i64; 1757} 1758 1759def atomic_load_zext_8 : 1760 PatFrag<(ops node:$ptr), (atomic_load_zext node:$ptr)> { 1761 let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic? 1762 let MemoryVT = i8; 1763} 1764 1765def atomic_load_zext_16 : 1766 PatFrag<(ops node:$ptr), (atomic_load_zext node:$ptr)> { 1767 let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic? 1768 let MemoryVT = i16; 1769} 1770 1771def atomic_load_sext_8 : 1772 PatFrag<(ops node:$ptr), (atomic_load_sext node:$ptr)> { 1773 let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic? 1774 let MemoryVT = i8; 1775} 1776 1777def atomic_load_sext_16 : 1778 PatFrag<(ops node:$ptr), (atomic_load_sext node:$ptr)> { 1779 let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic? 1780 let MemoryVT = i16; 1781} 1782 1783// Atomic load which zeroes or anyextends the high bits. 1784def atomic_load_az_8 : PatFrags<(ops node:$op), 1785 [(atomic_load_8 node:$op), 1786 (atomic_load_zext_8 node:$op)]>; 1787 1788// Atomic load which zeroes or anyextends the high bits. 1789def atomic_load_az_16 : PatFrags<(ops node:$op), 1790 [(atomic_load_16 node:$op), 1791 (atomic_load_zext_16 node:$op)]>; 1792 1793def nonext_masked_gather : 1794 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1795 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1796 return cast<MaskedGatherSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 1797}]>; 1798 1799// Any extending masked gather fragments. 1800def ext_masked_gather_i8 : 1801 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1802 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1803 auto MGN = cast<MaskedGatherSDNode>(N); 1804 return MGN->getExtensionType() == ISD::EXTLOAD && 1805 MGN->getMemoryVT().getScalarType() == MVT::i8; 1806}]>; 1807def ext_masked_gather_i16 : 1808 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1809 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1810 auto MGN = cast<MaskedGatherSDNode>(N); 1811 return MGN->getExtensionType() == ISD::EXTLOAD && 1812 MGN->getMemoryVT().getScalarType() == MVT::i16; 1813}]>; 1814def ext_masked_gather_i32 : 1815 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1816 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1817 auto MGN = cast<MaskedGatherSDNode>(N); 1818 return MGN->getExtensionType() == ISD::EXTLOAD && 1819 MGN->getMemoryVT().getScalarType() == MVT::i32; 1820}]>; 1821 1822// Sign extending masked gather fragments. 1823def sext_masked_gather_i8 : 1824 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1825 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1826 auto MGN = cast<MaskedGatherSDNode>(N); 1827 return MGN->getExtensionType() == ISD::SEXTLOAD && 1828 MGN->getMemoryVT().getScalarType() == MVT::i8; 1829}]>; 1830def sext_masked_gather_i16 : 1831 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1832 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1833 auto MGN = cast<MaskedGatherSDNode>(N); 1834 return MGN->getExtensionType() == ISD::SEXTLOAD && 1835 MGN->getMemoryVT().getScalarType() == MVT::i16; 1836}]>; 1837def sext_masked_gather_i32 : 1838 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1839 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1840 auto MGN = cast<MaskedGatherSDNode>(N); 1841 return MGN->getExtensionType() == ISD::SEXTLOAD && 1842 MGN->getMemoryVT().getScalarType() == MVT::i32; 1843}]>; 1844 1845// Zero extending masked gather fragments. 1846def zext_masked_gather_i8 : 1847 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1848 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1849 auto MGN = cast<MaskedGatherSDNode>(N); 1850 return MGN->getExtensionType() == ISD::ZEXTLOAD && 1851 MGN->getMemoryVT().getScalarType() == MVT::i8; 1852}]>; 1853def zext_masked_gather_i16 : 1854 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1855 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1856 auto MGN = cast<MaskedGatherSDNode>(N); 1857 return MGN->getExtensionType() == ISD::ZEXTLOAD && 1858 MGN->getMemoryVT().getScalarType() == MVT::i16; 1859}]>; 1860def zext_masked_gather_i32 : 1861 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1862 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1863 auto MGN = cast<MaskedGatherSDNode>(N); 1864 return MGN->getExtensionType() == ISD::ZEXTLOAD && 1865 MGN->getMemoryVT().getScalarType() == MVT::i32; 1866}]>; 1867 1868// Any/Zero extending masked gather fragments. 1869def azext_masked_gather_i8 : 1870 PatFrags<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1871 [(ext_masked_gather_i8 node:$def, node:$pred, node:$ptr, node:$idx), 1872 (zext_masked_gather_i8 node:$def, node:$pred, node:$ptr, node:$idx)]>; 1873def azext_masked_gather_i16 : 1874 PatFrags<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1875 [(ext_masked_gather_i16 node:$def, node:$pred, node:$ptr, node:$idx), 1876 (zext_masked_gather_i16 node:$def, node:$pred, node:$ptr, node:$idx)]>; 1877def azext_masked_gather_i32 : 1878 PatFrags<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1879 [(ext_masked_gather_i32 node:$def, node:$pred, node:$ptr, node:$idx), 1880 (zext_masked_gather_i32 node:$def, node:$pred, node:$ptr, node:$idx)]>; 1881 1882def nontrunc_masked_scatter : 1883 PatFrag<(ops node:$val, node:$pred, node:$ptr, node:$idx), 1884 (masked_scatter node:$val, node:$pred, node:$ptr, node:$idx), [{ 1885 return !cast<MaskedScatterSDNode>(N)->isTruncatingStore(); 1886}]>; 1887 1888// Truncating masked scatter fragments. 1889def trunc_masked_scatter_i8 : 1890 PatFrag<(ops node:$val, node:$pred, node:$ptr, node:$idx), 1891 (masked_scatter node:$val, node:$pred, node:$ptr, node:$idx), [{ 1892 auto MSN = cast<MaskedScatterSDNode>(N); 1893 return MSN->isTruncatingStore() && 1894 MSN->getMemoryVT().getScalarType() == MVT::i8; 1895}]>; 1896def trunc_masked_scatter_i16 : 1897 PatFrag<(ops node:$val, node:$pred, node:$ptr, node:$idx), 1898 (masked_scatter node:$val, node:$pred, node:$ptr, node:$idx), [{ 1899 auto MSN = cast<MaskedScatterSDNode>(N); 1900 return MSN->isTruncatingStore() && 1901 MSN->getMemoryVT().getScalarType() == MVT::i16; 1902}]>; 1903def trunc_masked_scatter_i32 : 1904 PatFrag<(ops node:$val, node:$pred, node:$ptr, node:$idx), 1905 (masked_scatter node:$val, node:$pred, node:$ptr, node:$idx), [{ 1906 auto MSN = cast<MaskedScatterSDNode>(N); 1907 return MSN->isTruncatingStore() && 1908 MSN->getMemoryVT().getScalarType() == MVT::i32; 1909}]>; 1910 1911 1912def atomic_store_8 : 1913 PatFrag<(ops node:$val, node:$ptr), 1914 (atomic_store node:$val, node:$ptr)> { 1915 let IsAtomic = true; 1916 let MemoryVT = i8; 1917} 1918 1919def atomic_store_16 : 1920 PatFrag<(ops node:$val, node:$ptr), 1921 (atomic_store node:$val, node:$ptr)> { 1922 let IsAtomic = true; 1923 let MemoryVT = i16; 1924} 1925 1926def atomic_store_32 : 1927 PatFrag<(ops node:$val, node:$ptr), 1928 (atomic_store node:$val, node:$ptr)> { 1929 let IsAtomic = true; 1930 let MemoryVT = i32; 1931} 1932 1933def atomic_store_64 : 1934 PatFrag<(ops node:$val, node:$ptr), 1935 (atomic_store node:$val, node:$ptr)> { 1936 let IsAtomic = true; 1937 let MemoryVT = i64; 1938} 1939 1940//===----------------------------------------------------------------------===// 1941// Selection DAG Pattern Support. 1942// 1943// Patterns are what are actually matched against by the target-flavored 1944// instruction selection DAG. Instructions defined by the target implicitly 1945// define patterns in most cases, but patterns can also be explicitly added when 1946// an operation is defined by a sequence of instructions (e.g. loading a large 1947// immediate value on RISC targets that do not support immediates as large as 1948// their GPRs). 1949// 1950 1951class Pattern<dag patternToMatch, list<dag> resultInstrs> { 1952 dag PatternToMatch = patternToMatch; 1953 list<dag> ResultInstrs = resultInstrs; 1954 list<Predicate> Predicates = []; // See class Instruction in Target.td. 1955 int AddedComplexity = 0; // See class Instruction in Target.td. 1956} 1957 1958// Pat - A simple (but common) form of a pattern, which produces a simple result 1959// not needing a full list. 1960class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 1961 1962//===----------------------------------------------------------------------===// 1963// Complex pattern definitions. 1964// 1965 1966// Complex patterns, e.g. X86 addressing mode, requires pattern matching code 1967// in C++. Ty is the type of return value; NumOperands is the number of operands 1968// returned by the select function; SelectFunc is the name of the function used 1969// to pattern match the max. pattern; RootNodes are the list of possible root nodes 1970// of the sub-dags to match. 1971// e.g. X86 addressing mode - def addr : ComplexPattern<iPTR, 4, "SelectAddr", [add]>; 1972// 1973class ComplexPattern<ValueType ty, int numops, string fn, 1974 list<SDNode> roots = [], list<SDNodeProperty> props = [], 1975 int complexity = -1> { 1976 ValueType Ty = ty; 1977 int NumOperands = numops; 1978 string SelectFunc = fn; 1979 list<SDNode> RootNodes = roots; 1980 list<SDNodeProperty> Properties = props; 1981 int Complexity = complexity; 1982} 1983