| /freebsd/contrib/one-true-awk/ |
| H A D | awk.h | 151 #define FSIN 9 macro
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| H A D | lex.c | 85 { "sin", FSIN, BLTIN },
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| H A D | run.c | 2099 case FSIN: in bltin()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | ZOSLibcallNames.def | 25 HANDLE_LIBCALL(SIN_F32, "@@FSIN@B")
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 96 DAG_FUNCTION(sin, 1, 1, experimental_constrained_sin, FSIN)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 932 FSIN, enumerator
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| H A D | BasicTTIImpl.h | 1881 ISD = ISD::FSIN; in getTypeBasedIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 95 setOperationAction({ISD::FCOS, ISD::FSIN}, MVT::f32, Custom); in R600TargetLowering()
409 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
701 case ISD::FSIN: in LowerTrig()
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| H A D | AMDGPUISelLowering.cpp | 486 ISD::FSQRT, ISD::FSIN, ISD::FSUB, in AMDGPUTargetLowering()
613 case ISD::FSIN: in fnegFoldsIntoOpcode()
4836 case ISD::FSIN: in performFNegCombine()
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| H A D | SIISelLowering.cpp | 211 ISD::FSIN, ISD::FCOS, ISD::FPOW, ISD::FPOWI, in SITargetLowering()
539 setOperationAction({ISD::FSIN, ISD::FCOS, ISD::FDIV}, MVT::f32, Custom); in SITargetLowering()
599 ISD::FSIN, ISD::FROUND, ISD::FPTRUNC_ROUND}, in SITargetLowering()
5542 case ISD::FSIN: in LowerOperation()
10981 case ISD::FSIN: in LowerTrig()
12391 case ISD::FSIN: in isCanonicalized()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 204 case ISD::FSIN: return "fsin"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 130 case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break; in SoftenFloatResult()
1351 case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break; in ExpandFloatResult()
2417 case ISD::FSIN: in PromoteFloatResult()
2826 case ISD::FSIN: in SoftPromoteHalfResult()
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| H A D | LegalizeDAG.cpp | 2306 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN in useSinCos()
2307 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3569 case ISD::FSIN: in ExpandNode()
4424 case ISD::FSIN: in ConvertNodeToLibcall()
5363 case ISD::FSIN: in PromoteNode()
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| H A D | LegalizeVectorOps.cpp | 393 case ISD::FSIN: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 108 case ISD::FSIN: in ScalarizeVectorResult()
1110 case ISD::FSIN: in SplitVectorResult()
4283 case ISD::FSIN: in WidenVectorResult()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 928 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
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| H A D | X86InstrFPStack.td | 658 def FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1808 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1813 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1818 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 120 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, in CSKYTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1589 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1634 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 181 setOperationAction(ISD::FSIN, MVT::f32, Expand); in LoongArchTargetLowering()
214 setOperationAction(ISD::FSIN, MVT::f64, Expand); in LoongArchTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 389 setOperationAction(ISD::FSIN , MVT::f64, Expand); in PPCTargetLowering()
394 setOperationAction(ISD::FSIN , MVT::f32, Expand); in PPCTargetLowering()
403 setOperationAction(ISD::FSIN , MVT::f64, Custom); in PPCTargetLowering()
409 setOperationAction(ISD::FSIN , MVT::f32, Custom); in PPCTargetLowering()
851 setOperationAction(ISD::FSIN, VT, Expand); in PPCTargetLowering()
1180 setOperationAction(ISD::FSIN, MVT::f128, Expand); in PPCTargetLowering()
11604 case ISD::FSIN: return lowerSin(Op, DAG); in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 427 setOperationAction(ISD::FSIN, MVT::f32, Expand); in MipsTargetLowering()
428 setOperationAction(ISD::FSIN, MVT::f64, Expand); in MipsTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 366 setOperationAction(ISD::FSIN, VT, Expand); in addMVEVectorTypes()
876 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); in ARMTargetLowering()
898 setOperationAction(ISD::FSIN, MVT::v4f32, Expand); in ARMTargetLowering()
915 setOperationAction(ISD::FSIN, MVT::v2f32, Expand); in ARMTargetLowering()
1057 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
1457 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
1458 setOperationAction(ISD::FSIN, MVT::f32, Expand); in ARMTargetLowering()
1541 setOperationAction(ISD::FSIN, MVT::f16, Promote); in ARMTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 125 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
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