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Searched refs:HasBaseReg (Results 1 – 25 of 31) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AsmPrinter.cpp382 bool HasBaseReg = BaseReg.getReg() != 0; in PrintLeaMemReference() local
383 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in PrintLeaMemReference()
385 HasBaseReg = false; in PrintLeaMemReference()
388 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in PrintLeaMemReference()
413 if (HasBaseReg) in PrintLeaMemReference()
480 bool HasBaseReg = BaseReg.getReg() != 0; in PrintIntelMemReference() local
481 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in PrintIntelMemReference()
483 HasBaseReg = false; in PrintIntelMemReference()
488 HasBaseReg = false; in PrintIntelMemReference()
500 if (HasBaseReg) { in PrintIntelMemReference()
[all …]
H A DX86TargetTransformInfo.h254 int64_t BaseOffset, bool HasBaseReg,
H A DX86TargetTransformInfo.cpp6654 bool HasBaseReg, int64_t Scale, in getScalingFactorCost() argument
6677 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp363 bool HasBaseReg = false; member
483 HasBaseReg = true; in initialMatch()
489 HasBaseReg = true; in initialMatch()
639 if (HasBaseReg && BaseRegs.empty()) { in print()
642 } else if (!HasBaseReg && !BaseRegs.empty()) { in print()
1844 bool HasBaseReg) { in isAlwaysFoldable() argument
1854 if (!HasBaseReg && Scale == 1) { in isAlwaysFoldable()
1856 HasBaseReg = true; in isAlwaysFoldable()
1867 bool HasBaseReg) { in isAlwaysFoldable() argument
3437 F.HasBaseReg = true; in InsertSupplementalFormula()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DTargetTransformInfoImpl.h222 bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
318 int64_t BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
322 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, in getScalingFactorCost()
1029 bool HasBaseReg = (BaseGV == nullptr); in getGEPCost() local
1092 BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale, in getGEPCost()
H A DTargetTransformInfo.h712 bool HasBaseReg, int64_t Scale,
821 int64_t BaseOffset, bool HasBaseReg,
1823 int64_t BaseOffset, bool HasBaseReg,
1860 bool HasBaseReg, int64_t Scale,
2279 bool HasBaseReg, int64_t Scale, unsigned AddrSpace, in isLegalAddressingMode() argument
2281 return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, in isLegalAddressingMode()
2361 int64_t BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
2364 return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, in getScalingFactorCost()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp404 bool HasBaseReg, int64_t Scale, in isLegalAddressingMode() argument
407 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in isLegalAddressingMode()
521 Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
524 Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace); in getScalingFactorCost()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h335 bool HasBaseReg, int64_t Scale,
340 AM.HasBaseReg = HasBaseReg;
399 int64_t BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
404 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
H A DTargetLowering.h2691 bool HasBaseReg = false; member
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPerfHintAnalysis.cpp262 AM.HasBaseReg = !AM.BaseGV; in visit()
H A DSILoadStoreOptimizer.cpp2216 AM.HasBaseReg = true; in promoteConstantOffsetToImm()
2241 AM.HasBaseReg = true; in promoteConstantOffsetToImm()
H A DSIISelLowering.cpp1504 if (AM.HasBaseReg) { in isLegalMUBUFAddressingMode()
1572 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
1596 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
11146 AM.HasBaseReg = true; in performSHLPtrCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.h305 int64_t BaseOffset, bool HasBaseReg,
H A DARMTargetTransformInfo.cpp2567 bool HasBaseReg, int64_t Scale, in getScalingFactorCost() argument
2572 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.h409 int64_t BaseOffset, bool HasBaseReg,
H A DAArch64TargetTransformInfo.cpp4039 int64_t BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
4051 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
H A DAArch64ISelLowering.cpp16242 if (AMode.HasBaseReg && AMode.BaseOffs && AMode.Scale) in isLegalAddressingMode()
16248 if (AM.Scale && !AM.HasBaseReg) { in isLegalAddressingMode()
16250 AM.HasBaseReg = true; in isLegalAddressingMode()
16253 AM.HasBaseReg = true; in isLegalAddressingMode()
16261 if (!AM.HasBaseReg) in isLegalAddressingMode()
16268 return AM.HasBaseReg && !AM.BaseOffs && in isLegalAddressingMode()
16272 return AM.HasBaseReg && !AM.BaseOffs && !AM.Scale; in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp3758 !NewAddrMode.HasBaseReg); in addNewAddrMode()
4901 if (AddrMode.HasBaseReg) { in matchOperationAddr()
4906 AddrMode.HasBaseReg = true; in matchOperationAddr()
4917 if (AddrMode.HasBaseReg) in matchOperationAddr()
4919 AddrMode.HasBaseReg = true; in matchOperationAddr()
5053 if (!AddrMode.HasBaseReg) { in matchAddr()
5054 AddrMode.HasBaseReg = true; in matchAddr()
5059 AddrMode.HasBaseReg = false; in matchAddr()
6222 AddrMode.HasBaseReg = true; in splitLargeGEPOffsets()
H A DTargetLoweringBase.cpp1983 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1988 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp931 if (!AM.HasBaseReg) // allow "r+i". in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1064 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) { in isLegalAddressingMode()
1076 if (AM.BaseGV == nullptr && AM.HasBaseReg && AM.Scale == 0 && in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp965 AM.HasBaseReg = true; in canFoldInAddressingMode()
1590 AMNew.HasBaseReg = true; in matchPtrAddImmedChain()
1593 AMOld.HasBaseReg = true; in matchPtrAddImmedChain()
4553 AM.HasBaseReg = true; in reassociationCanBreakAddressingModePattern()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp4888 if (!AM.HasBaseReg) in isLegalAddressingMode()
4894 if (AM.HasBaseReg && AM.BaseOffs != 0) in isLegalAddressingMode()
4900 if (AM.HasBaseReg || AM.BaseOffs) in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1795 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4987 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale; in isLegalAddressingMode()
4994 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed. in isLegalAddressingMode()

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