Searched refs:LegalOperations (Results 1 – 8 of 8) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 1589 if (!LegalOperations) in PromoteIntBinOp() 1657 if (!LegalOperations) in PromoteIntShiftOp() 1706 if (!LegalOperations) in PromoteExtend() 1734 if (!LegalOperations) in PromoteLoad() 6440 if (LegalOperations && in isAndLoadExtLoad() 7367 if (!LegalOperations) in MatchBSwapHWordLow() 7637 if (!LegalOperations) in MatchBSwapHWord() 9204 if (LegalOperations && in MatchLoadCombine() 22167 if (LegalOperations && in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts() 23214 if (LegalOperations) in convertBuildVecZextToZext() [all …]
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H A D | TargetLowering.cpp | 1842 (!TLO.LegalOperations() || isOperationLegal(ISD::SHL, HalfVT))) { in SimplifyDemandedBits() 1950 (!TLO.LegalOperations() || isOperationLegal(ISD::SRL, HalfVT)) && in SimplifyDemandedBits() 2031 if (!TLO.LegalOperations() || in SimplifyDemandedBits() 2188 if ((!TLO.LegalOperations() || isOperationLegal(ISD::SHL, VT)) && in SimplifyDemandedBits() 2193 if ((!TLO.LegalOperations() || isOperationLegal(ISD::SRL, VT)) && in SimplifyDemandedBits() 2290 if (!TLO.LegalOperations() || isOperationLegal(ShiftOpcode, VT)) { in SimplifyDemandedBits() 2411 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) in SimplifyDemandedBits() 2468 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) in SimplifyDemandedBits() 2486 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) { in SimplifyDemandedBits() 2655 if (!TLO.LegalOperations() && !VT.isVector() && !SrcVT.isVector() && in SimplifyDemandedBits()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.h | 58 bool LegalOperations) const override { in canCombineTruncStore() argument
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H A D | AMDGPUISelLowering.h | 200 bool LegalOperations, bool ForCodeSize,
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H A D | AMDGPUISelLowering.cpp | 868 SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, in getNegatedExpression() argument 884 SDValue NegSrc = getNegatedExpression(Src, DAG, LegalOperations, in getNegatedExpression() 894 return TargetLowering::getNegatedExpression(Op, DAG, LegalOperations, in getNegatedExpression()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.h | 1086 bool LegalOperations, bool ForCodeSize,
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H A D | X86ISelLowering.cpp | 51612 bool LegalOperations = !DCI.isBeforeLegalizeOps(); in combineFneg() local 51614 TLI.getNegatedExpression(Arg, DAG, LegalOperations, CodeSize)) in combineFneg() 51621 bool LegalOperations, in getNegatedExpression() argument 51659 Op.getOperand(i), DAG, LegalOperations, ForCodeSize, Depth + 1); in getNegatedExpression() 51677 getNegatedExpression(Op.getOperand(0), DAG, LegalOperations, in getNegatedExpression() 51683 return TargetLowering::getNegatedExpression(Op, DAG, LegalOperations, in getNegatedExpression() 52764 bool LegalOperations = !DCI.isBeforeLegalizeOps(); in combineFMA() local 52765 if (SDValue NegV = TLI.getCheaperNegatedExpression(V, DAG, LegalOperations, in combineFMA() 52776 Vec, DAG, LegalOperations, CodeSize)) { in combineFMA() 52825 bool LegalOperations = !DCI.isBeforeLegalizeOps(); in combineFMADDSUB() local [all …]
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetLowering.h | 3811 bool LegalOperations() const { return LegalOps; } in LegalOperations() function
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