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Searched refs:MCII (Results 1 – 25 of 106) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h48 MCInstrInfo const &MCII; variable
55 PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst);
179 unsigned getCVIResources(MCInstrInfo const &MCII,
186 unsigned getOtherReservedSlots(MCInstrInfo const &MCII,
223 bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI);
231 bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI);
237 bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI);
252 bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI);
254 bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI);
298 bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI);
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H A DHexagonMCInstrInfo.cpp41 : MCII(MCII), BundleCurrent(Inst.begin() + in PacketIterator()
47 : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()), in PacketIterator()
63 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) { in operator ++()
165 HexagonMCShuffle(Context, true, MCII, STI, MCB); in canonicalizePacketImpl()
237 if (isConstExtended(MCII, MCI)) in extendIfNeeded()
238 addConstExtender(Context, MCII, MCB, MCI); in extendIfNeeded()
257 return MCII.get(MCI.getOpcode()); in getDesc()
376 return MCII.getName(MCI.getOpcode()); in getName()
646 const uint64_t V = getType(MCII, MCI); in isHVX()
939 if (!isPredicated(MCII, MCI)) in predicateInfo()
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H A DHexagonMCChecker.cpp58 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) { in init()
70 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && in initReg()
77 if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) in initReg()
200 : Context(Context), MCB(mcb), RI(ri), MCII(MCII), STI(STI), in HexagonMCChecker()
208 : Context(Other.Context), MCB(Other.MCB), RI(Other.RI), MCII(Other.MCII), in HexagonMCChecker()
273 if (HexagonMCInstrInfo::isFloat(MCII, ID)) in isNeitherAnorX()
299 if (HexagonMCInstrInfo::isSoloAX(MCII, I)) { in checkAXOK()
349 if (HexagonMCInstrInfo::isCofMax1(MCII, I)) { in checkCOFMax1()
589 if (HexagonMCInstrInfo::isCVINew(MCII, I) && in checkRegisterCurDefs()
695 if (HexagonMCInstrInfo::isSolo(MCII, I)) { in checkSolo()
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H A DHexagonMCShuffler.cpp39 LLVM_DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode()) in init()
41 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo()); in init()
44 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI)); in init()
63 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
66 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI)); in init()
106 HexagonMCShuffler MCS(Context, ReportErrors, MCII, STI, MCB); in HexagonMCShuffle()
130 bool llvm::HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII, in HexagonMCShuffle() argument
172 HexagonMCShuffler MCS(Context, false, MCII, STI, MCB); in HexagonMCShuffle()
179 bool llvm::HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII, in HexagonMCShuffle() argument
190 bool bhasDuplex = HexagonMCInstrInfo::hasDuplex(MCII, MCB); in HexagonMCShuffle()
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H A DHexagonShuffler.cpp131 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); in HexagonCVIResource()
169 MCInstrInfo const &MCII, in HexagonShuffler() argument
171 : Context(Context), BundleFlags(), MCII(MCII), STI(STI), in HexagonShuffler()
184 HexagonInstr PI(MCII, STI, &ID, Extender, S); in append()
373 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { in restrictStoreLoadOrder()
406 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()) { in restrictStoreLoadOrder()
459 if (HexagonMCInstrInfo::isRestrictSlot1AOK(MCII, ID)) in GetPacketSummary()
464 if (HexagonMCInstrInfo::prefersSlot3(MCII, ID)) { in GetPacketSummary()
476 switch (HexagonMCInstrInfo::getType(MCII, ID)) { in GetPacketSummary()
502 if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn()) in GetPacketSummary()
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H A DHexagonMCShuffler.h32 MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffler() argument
34 : HexagonShuffler(Context, ReportErrors, MCII, STI) { in HexagonMCShuffler()
39 MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffler() argument
41 : HexagonShuffler(Context, ReportErrors, MCII, STI) { in HexagonMCShuffler()
59 MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
61 bool HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
64 bool HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
H A DHexagonMCCodeEmitter.cpp342 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI); in parseBits()
621 unsigned IType = HexagonMCInstrInfo::getType(MCII, MI); in getExprOpValue()
678 FixupKind = getFixupNoBits(MCII, MI, MO, VarKind); in getExprOpValue()
719 if (HexagonMCInstrInfo::isNewValue(MCII, MI) && in getMachineOpValue()
740 if (HexagonMCInstrInfo::isVector(MCII, Inst)) { in getMachineOpValue()
744 if (HexagonMCInstrInfo::hasNewValue(MCII, Inst)) in getMachineOpValue()
746 if (HexagonMCInstrInfo::hasNewValue2(MCII, Inst)) in getMachineOpValue()
752 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) { in getMachineOpValue()
756 assert(HexagonMCInstrInfo::isPredicated(MCII, MI) && in getMachineOpValue()
759 HexagonMCInstrInfo::isPredicatedTrue(MCII, MI)) in getMachineOpValue()
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H A DHexagonAsmBackend.cpp45 std::unique_ptr <MCInstrInfo> MCII; member in __anonc65b099f0111::HexagonAsmBackend
66 relaxedCnt(0), MCII(T.createMCInstrInfo()), RelaxTarget(new MCInst *), in HexagonAsmBackend()
539 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI); in isInstRelaxable()
542 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ || in isInstRelaxable()
543 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCJ && in isInstRelaxable()
549 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) { in isInstRelaxable()
552 HMI.getOperand(HexagonMCInstrInfo::getExtendableOp(*MCII, HMI)); in isInstRelaxable()
675 *MCII, CrntHMI, in relaxInstruction()
676 HexagonMCInstrInfo::getExtendableOperand(*MCII, CrntHMI)); in relaxInstruction()
745 Context, *MCII, *RF.getSubtargetInfo(), Inst, in finishLayout()
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H A DHexagonShuffler.h87 HexagonCVIResource(MCInstrInfo const &MCII,
107 HexagonInstr(MCInstrInfo const &MCII, in HexagonInstr() argument
110 : ID(id), Extender(Extender), Core(s), CVI(MCII, STI, s, id){}; in HexagonInstr()
164 MCInstrInfo const &MCII; variable
195 MCInstrInfo const &MCII, MCSubtargetInfo const &STI);
228 return (*Pred)(MCII, Inst); in HasInstWith()
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/
H A DCustomBehaviour.h39 const MCInstrInfo &MCII; variable
42 InstrPostProcess(const MCSubtargetInfo &STI, const MCInstrInfo &MCII) in InstrPostProcess() argument
43 : STI(STI), MCII(MCII) {} in InstrPostProcess()
70 const MCInstrInfo &MCII; variable
74 const MCInstrInfo &MCII) in CustomBehaviour() argument
75 : STI(STI), SrcMgr(SrcMgr), MCII(MCII) {} in CustomBehaviour()
144 const MCInstrInfo &MCII; variable
147 InstrumentManager(const MCSubtargetInfo &STI, const MCInstrInfo &MCII) in InstrumentManager() argument
148 : STI(STI), MCII(MCII) {} in InstrumentManager()
175 virtual unsigned getSchedClassID(const MCInstrInfo &MCII, const MCInst &MCI,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.h21 std::unique_ptr<const MCInstrInfo> const MCII; variable
25 MCInstrInfo const *MCII) in AArch64Disassembler() argument
26 : MCDisassembler(STI, Ctx), MCII(MCII) {} in AArch64Disassembler()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCCodeEmitter.cpp37 MCInstrInfo const &MCII; member in llvm::MSP430MCCodeEmitter
74 MSP430MCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) in MSP430MCCodeEmitter() argument
75 : Ctx(ctx), MCII(MCII) {} in MSP430MCCodeEmitter()
86 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
204 MCCodeEmitter *createMSP430MCCodeEmitter(const MCInstrInfo &MCII, in createMSP430MCCodeEmitter() argument
206 return new MSP430MCCodeEmitter(Ctx, MCII); in createMSP430MCCodeEmitter()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCCodeEmitter.cpp35 const MCInstrInfo &MCII; member in __anonfa1974450111::SystemZMCCodeEmitter
39 SystemZMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx) in SystemZMCCodeEmitter() argument
40 : MCII(MCII), Ctx(Ctx) {} in SystemZMCCodeEmitter()
138 unsigned Size = MCII.get(MI.getOpcode()).getSize(); in encodeInstruction()
168 unsigned MIBitSize = MCII.get(MI.getOpcode()).getSize() * 8; in getImmOpValue()
224 MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII, in createSystemZMCCodeEmitter() argument
226 return new SystemZMCCodeEmitter(MCII, Ctx); in createSystemZMCCodeEmitter()
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp70 const MCInstrInfo &MCII, in computeInstrLatency() argument
72 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in computeInstrLatency()
79 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in computeInstrLatency()
113 const MCInstrInfo &MCII, in getReciprocalThroughput() argument
115 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in getReciprocalThroughput()
125 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in getReciprocalThroughput()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCCodeEmitter.cpp41 const MCInstrInfo &MCII; member in __anon3a3260630111::WebAssemblyMCCodeEmitter
53 WebAssemblyMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx) in WebAssemblyMCCodeEmitter() argument
54 : MCII(MCII), Ctx{Ctx} {} in WebAssemblyMCCodeEmitter()
58 MCCodeEmitter *llvm::createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII, in createWebAssemblyMCCodeEmitter() argument
60 return new WebAssemblyMCCodeEmitter(MCII, Ctx); in createWebAssemblyMCCodeEmitter()
92 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVMCCodeEmitter.cpp32 const MCInstrInfo &MCII; member in __anon8d15560f0111::SPIRVMCCodeEmitter
35 SPIRVMCCodeEmitter(const MCInstrInfo &mcii) : MCII(mcii) {} in SPIRVMCCodeEmitter()
53 MCCodeEmitter *llvm::createSPIRVMCCodeEmitter(const MCInstrInfo &MCII, in createSPIRVMCCodeEmitter() argument
55 return new SPIRVMCCodeEmitter(MCII); in createSPIRVMCCodeEmitter()
119 if (hasType(MI, MCII)) in encodeInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp64 const MCInstrInfo &MCII) in AMDGPUCustomBehaviour() argument
65 : CustomBehaviour(STI, SrcMgr, MCII) { in AMDGPUCustomBehaviour()
201 << MCII.getName(Opcode) << " will be completely " in computeWaitCnt()
250 const MCInstrDesc &MCID = MCII.get(Opcode); in generateWaitCntInfo()
326 const MCInstrDesc &MCID = MCII.get(Opcode); in isGWS()
344 const MCInstrInfo &MCII) { in createAMDGPUCustomBehaviour() argument
345 return new AMDGPUCustomBehaviour(STI, SrcMgr, MCII); in createAMDGPUCustomBehaviour()
350 const MCInstrInfo &MCII) { in createAMDGPUInstrPostProcess() argument
351 return new AMDGPUInstrPostProcess(STI, MCII); in createAMDGPUInstrPostProcess()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/
H A DRISCVCustomBehaviour.cpp241 const MCInstrInfo &MCII, const MCInst &MCI, in getSchedClassID() argument
244 unsigned SchedClassID = MCII.get(Opcode).getSchedClass(); in getSchedClassID()
287 << MCII.getName(Opcode) in getSchedClassID()
297 << MCII.getName(Opcode) << ", LMUL=" << LI->getData() in getSchedClassID()
300 << " with " << MCII.getName(RVV->Pseudo) << '\n'); in getSchedClassID()
301 return MCII.get(RVV->Pseudo).getSchedClass(); in getSchedClassID()
312 const MCInstrInfo &MCII) { in createRISCVInstrumentManager() argument
313 return new RISCVInstrumentManager(STI, MCII); in createRISCVInstrumentManager()
H A DRISCVCustomBehaviour.h55 RISCVInstrumentManager(const MCSubtargetInfo &STI, const MCInstrInfo &MCII) in RISCVInstrumentManager() argument
56 : InstrumentManager(STI, MCII) {} in RISCVInstrumentManager()
69 getSchedClassID(const MCInstrInfo &MCII, const MCInst &MCI,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.h38 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
66 bool isHForm(const MCInst &MI, const MCInstrInfo *MCII);
67 bool isQForm(const MCInst &MI, const MCInstrInfo *MCII);
68 bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII);
/freebsd/contrib/llvm-project/llvm/tools/llvm-mca/
H A Dllvm-mca.cpp407 assert(MCII && "Unable to create instruction info!"); in main()
410 TheTarget->createMCInstrAnalysis(MCII.get())); in main()
436 *MCII); in main()
463 TheTarget->createInstrumentManager(*STI, *MCII)); in main()
468 IM = std::make_unique<mca::InstrumentManager>(*STI, *MCII); in main()
478 *MCII, *IM); in main()
531 TheTarget->createInstrPostProcess(*STI, *MCII)); in main()
536 IPP = std::make_unique<mca::InstrPostProcess>(*STI, *MCII); in main()
540 mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get(), *IM); in main()
553 TheTarget->createMCCodeEmitter(*MCII, ACtx)); in main()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600MCCodeEmitter.cpp33 const MCInstrInfo &MCII; member in __anon1584396d0111::R600MCCodeEmitter
37 : MRI(mri), MCII(mcii) {} in R600MCCodeEmitter()
81 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII, in createR600MCCodeEmitter() argument
83 return new R600MCCodeEmitter(MCII, *Ctx.getRegisterInfo()); in createR600MCCodeEmitter()
90 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
161 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) in getMachineOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCCodeEmitter.h39 AVRMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx) in AVRMCCodeEmitter() argument
40 : MCII(MCII), Ctx(Ctx) {} in AVRMCCodeEmitter()
105 const MCInstrInfo &MCII; variable
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp45 std::unique_ptr<MCInstrInfo const> const MCII; member in __anon0bf4b43c0111::HexagonDisassembler
50 MCInstrInfo const *MCII) in HexagonDisassembler() argument
51 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *), in HexagonDisassembler()
65 MCInstrInfo MCII = *Disassembler.MCII; in fullValue() local
67 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) in fullValue()
200 HexagonMCChecker Checker(getContext(), *MCII, STI_, MI, in getInstruction()
469 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { in getSingleInstruction()
480 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); in getSingleInstruction()
500 if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { in getSingleInstruction()
532 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && in getSingleInstruction()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/MCTargetDesc/
H A DM68kMCCodeEmitter.cpp40 const MCInstrInfo &MCII; member in __anon43e5d4b30111::M68kMCCodeEmitter
68 : MCII(mcii), Ctx(ctx) {} in M68kMCCodeEmitter()
230 LLVM_DEBUG(dbgs() << "EncodeInstruction: " << MCII.getName(MI.getOpcode()) in encodeInstruction()
232 (void)MCII; in encodeInstruction()
250 MCCodeEmitter *llvm::createM68kMCCodeEmitter(const MCInstrInfo &MCII, in createM68kMCCodeEmitter() argument
252 return new M68kMCCodeEmitter(MCII, Ctx); in createM68kMCCodeEmitter()

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