| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | MVETailPredUtils.h | 111 MIB.addImm(0);
112 MIB.addImm(ARMCC::AL);
119 MIB.addImm(0);
120 MIB.addImm(ARMCC::AL);
130 MIB.addReg(ARM::CPSR);
154 MIB.addImm(ARMCC::AL);
155 MIB.addReg(0);
158 MIB.addReg(ARM::CPSR);
161 MIB.addReg(0);
176 MIB.addImm(0);
[all …]
|
| H A D | ARMInstructionSelector.cpp | 484 : MBB(*MIB->getParent()), InsertBefore(std::next(MIB->getIterator())), in InsertInfo()
529 const InsertInfo I(MIB); in selectCmp()
569 MIB->eraseFromParent(); in selectCmp()
649 MIB.addImm(0); in selectGlobal()
722 OffsetMIB = BuildMI(MBB, *MIB, MIB->getDebugLoc(), in selectGlobal()
727 OffsetMIB = BuildMI(MBB, *MIB, MIB->getDebugLoc(), in selectGlobal()
736 MIB->removeOperand(1); in selectGlobal()
800 MIB->eraseFromParent(); in selectSelect()
808 MIB.addImm(ShiftOpc); in selectShift()
1000 MIB->removeOperand(1); in select()
[all …]
|
| H A D | ARMExpandPseudoInsts.cpp | 659 MIB.add(MO); in ExpandVLD()
818 MIB.addImm(Lane); in ExpandLaneOp()
827 MIB.add(MO); in ExpandLaneOp()
852 MIB.add(VdSrc); in ExpandVTBL()
859 MIB.addReg(D0); in ExpandVTBL()
863 MIB.add(VmSrc); in ExpandVTBL()
1832 MIB.addImm(0); in ExpandCMP_SWAP()
2571 MIB = in ExpandMI()
2579 MIB = in ExpandMI()
2802 MIB.add(Dst); in ExpandMI()
[all …]
|
| H A D | Thumb2SizeReduction.cpp | 598 MIB.add(MI->getOperand(0)); in ReduceLoadStore()
599 MIB.add(MI->getOperand(1)); in ReduceLoadStore()
613 MIB.add(MO); in ReduceLoadStore()
658 MachineInstrBuilder MIB = in ReduceSpecial() local
832 MIB.add(MI->getOperand(0)); in ReduceTo2Addr()
843 MIB.add(MI->getOperand(i)); in ReduceTo2Addr()
928 MIB.add(MI->getOperand(0)); in ReduceToNarrow()
935 MIB.add(MI->getOperand(0)); in ReduceToNarrow()
937 MIB.add(MI->getOperand(0)); in ReduceToNarrow()
963 MIB.add(MO); in ReduceToNarrow()
[all …]
|
| H A D | ARMCallLowering.cpp | 92 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB) {} in ARMOutgoingValueHandler()
122 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
176 MachineInstrBuilder MIB; member
427 MachineInstrBuilder MIB) in CallReturnHandler()
428 : ARMIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
431 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
434 MachineInstrBuilder MIB; member
480 MIB.add(predOps(ARMCC::AL)); in lowerCall()
482 MIB.add(Info.Callee); in lowerCall()
489 *MIB.getInstr(), MIB->getDesc(), Info.Callee, CalleeIdx)); in lowerCall()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kExpandPseudo.cpp | 75 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI); in INITIALIZE_PASS() local
84 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8); in INITIALIZE_PASS()
86 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i8); in INITIALIZE_PASS()
88 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16); in INITIALIZE_PASS()
91 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i16, MVT::i8); in INITIALIZE_PASS()
93 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i8); in INITIALIZE_PASS()
95 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i16); in INITIALIZE_PASS()
185 return TII->ExpandCCR(MIB, /*IsToCCR=*/true); in INITIALIZE_PASS()
187 return TII->ExpandCCR(MIB, /*IsToCCR=*/false); in INITIALIZE_PASS()
241 MachineInstrBuilder MIB = in INITIALIZE_PASS() local
[all …]
|
| H A D | M68kInstrInfo.cpp | 376 MIB->eraseFromParent(); in ExpandMOVX_RR()
379 MIB->setDesc(get(Move)); in ExpandMOVX_RR()
433 MIB->eraseFromParent(); in ExpandMOVSZX_RR()
456 MIB->setDesc(Desc); in ExpandMOVSZX_RM()
487 MIB->eraseFromParent(); in ExpandPUSH_POP()
512 auto DL = MIB->getDebugLoc(); in ExpandMOVEM()
513 auto MI = MIB.getInstr(); in ExpandMOVEM()
540 .copyImplicitOps(*MIB); in ExpandMOVEM()
547 .copyImplicitOps(*MIB); in ExpandMOVEM()
550 MIB->eraseFromParent(); in ExpandMOVEM()
[all …]
|
| H A D | M68kInstrBuilder.h | 41 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument
42 return MIB.addImm(Offset); in addOffset()
49 addRegIndirectWithDisp(const MachineInstrBuilder &MIB, Register Reg, in addRegIndirectWithDisp() argument
51 return MIB.addImm(Offset).addReg(Reg, getKillRegState(IsKill)); in addRegIndirectWithDisp()
59 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
60 MachineInstr *MI = MIB;
72 return MIB.addImm(Offset).addFrameIndex(FI).addMemOperand(MMO);
76 addMemOperand(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
77 MachineInstr *MI = MIB;
89 return MIB.addMemOperand(MMO);
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 227 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(ShAmtReg); }}}; in selectShiftMask()
381 [=](MachineInstrBuilder &MIB) { MIB.add(RootDef->getOperand(1)); }, in selectAddrRegImm()
382 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, in selectAddrRegImm()
396 [=](MachineInstrBuilder &MIB) { MIB.add(LHSDef->getOperand(1)); }, in selectAddrRegImm()
397 [=](MachineInstrBuilder &MIB) { MIB.addImm(RHSC); }, in selectAddrRegImm()
400 return {{[=](MachineInstrBuilder &MIB) { MIB.add(LHS); }, in selectAddrRegImm()
401 [=](MachineInstrBuilder &MIB) { MIB.addImm(RHSC); }}}; in selectAddrRegImm()
407 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); }, in selectAddrRegImm()
408 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }}}; in selectAddrRegImm()
785 MIB.addImm(-CstVal); in renderNegImm()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrBuilder.h | 143 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument
157 addRegOffset(const MachineInstrBuilder &MIB, in addRegOffset() argument
172 addFullAddress(const MachineInstrBuilder &MIB, in addFullAddress() argument
177 MIB.addReg(AM.Base.Reg); in addFullAddress()
180 MIB.addFrameIndex(AM.Base.FrameIndex); in addFullAddress()
183 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
187 MIB.addImm(AM.Disp); in addFullAddress()
189 return MIB.addReg(0); in addFullAddress()
199 MachineInstr *MI = MIB;
211 return addOffset(MIB.addFrameIndex(FI), Offset)
[all …]
|
| H A D | X86FixupBWInsts.cpp | 297 MachineInstrBuilder MIB = in tryReplaceLoad() local
302 MIB.add(MI->getOperand(i)); in tryReplaceLoad()
304 MIB.setMemRefs(MI->memoperands()); in tryReplaceLoad()
314 return MIB; in tryReplaceLoad()
341 MachineInstrBuilder MIB = in tryReplaceCopy() local
349 MIB.add(Op); in tryReplaceCopy()
351 return MIB; in tryReplaceCopy()
369 MachineInstrBuilder MIB = in tryReplaceExtend() local
374 MIB.add(MI->getOperand(i)); in tryReplaceExtend()
376 MIB.setMemRefs(MI->memoperands()); in tryReplaceExtend()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 2084 MIB->tieOperands(0, MIB->getNumOperands() - 1); in selectImageIntrinsic()
3708 [=](MachineInstrBuilder &MIB) { MIB.add(Root); } in selectVCSRC()
3772 [=](MachineInstrBuilder &MIB) { MIB.add(Root); } in selectVSRC0()
3813 [=](MachineInstrBuilder &MIB) { MIB.add(Root); }, in selectVOP3OMods()
3870 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectVOP3NoMods()
3910 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PMods()
3925 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PModsDOT()
4145 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectSWMMACIndex8()
4167 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectSWMMACIndex16()
4180 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3OpSelMods()
[all …]
|
| H A D | AMDGPUCallLowering.cpp | 48 : OutgoingValueHandler(B, MRI), MIB(MIB) {} in AMDGPUOutgoingValueHandler()
50 MachineInstrBuilder MIB; member
169 : AMDGPUIncomingArgHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
175 MachineInstrBuilder MIB; member
1211 MIB.addImm(0); in lowerTailCall()
1229 MIB->getDesc(), MIB->getOperand(Idx), Idx)); in lowerTailCall()
1235 MIB.addRegMask(Mask); in lowerTailCall()
1320 MIRBuilder.insertInstr(MIB); in lowerTailCall()
1331 MIB->getDesc(), MIB->getOperand(0), 0)); in lowerTailCall()
1457 MIB.addRegMask(Mask); in lowerCall()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 593 MIB.addImm(SubIdx); in EmitSubregNode()
750 AddOperand(MIB, V, (*MIB).getNumOperands(), &DbgValDesc, VRBaseMap, in AddDbgValueLocationOps()
912 MIB.addMetadata(Var); in EmitDbgValueList()
913 MIB.addMetadata(Expr); in EmitDbgValueList()
915 return &*MIB; in EmitDbgValueList()
946 MIB.addImm(0U); in EmitDbgValueFromSingleOp()
948 MIB.addReg(0U); in EmitDbgValueFromSingleOp()
962 MIB.addMetadata(Label); in EmitDbgLabel()
964 return &*MIB; in EmitDbgLabel()
1302 MIB.addImm(ExtraInfo); in EmitSpecialNode()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CSEMIRBuilder.cpp | 127 MachineInstr *MIBInstr = MIB; in memoizeMI()
129 return MIB; in memoizeMI()
160 Observer->changingInstr(*MIB); in generateCopiesIfRequired()
161 MIB->setDebugLoc( in generateCopiesIfRequired()
164 Observer->changedInstr(*MIB); in generateCopiesIfRequired()
167 return MIB; in generateCopiesIfRequired()
285 getCSEInfo()->handleRemoveInst(&*MIB); in buildInstr()
286 return MIB; in buildInstr()
293 if (MIB) { in buildInstr()
321 if (MIB) { in buildConstant()
[all …]
|
| H A D | MachineIRBuilder.cpp | 46 return MIB; in insertInstr()
142 return MIB; in buildDynStackAlloc()
151 return MIB; in buildFrameIndex()
164 return MIB; in buildGlobalValue()
173 return MIB; in buildConstantPool()
400 return MIB; in buildBrCond()
428 return MIB; in buildLoadInstr()
458 return MIB; in buildStore()
802 return MIB; in buildIntrinsic()
822 return MIB; in buildIntrinsic()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPreLegalizer.cpp | 152 MIB.buildBitcast(Def, Source); in insertBitcasts()
223 MIB.setInsertPt(*Def->getParent(), in insertAssignInstr()
241 MIB.buildInstr(SPIRV::ASSIGN_TYPE) in insertAssignInstr()
378 MIB.setInsertPt(*MI.getParent(), in processInstr()
400 processInstr(MI, MIB, MRI, GR); in processInstrsWithTypeFolding()
639 MIB.setInsertPt(MBB, MBB.end()); in removeImplicitFallthroughs()
649 MachineIRBuilder MIB(MF); in runOnMachineFunction() local
652 insertBitcasts(MF, GR, MIB); in runOnMachineFunction()
653 generateAssignInstrs(MF, GR, MIB); in runOnMachineFunction()
654 processSwitches(MF, GR, MIB); in runOnMachineFunction()
[all …]
|
| H A D | SPIRVGlobalRegistry.cpp | 105 return MIB; in getOpTypeInt()
113 return MIB; in getOpTypeFloat()
133 return MIB; in getOpTypeVector()
178 MachineInstrBuilder MIB; in getOrCreateConstInt() local
261 MachineInstrBuilder MIB; in buildConstantFP() local
559 return MIB; in getOpTypeArray()
568 addStringImm(Name, MIB); in getOpTypeOpaque()
570 return MIB; in getOpTypeOpaque()
586 MIB.addUse(Ty); in getOpTypeStruct()
591 return MIB; in getOpTypeStruct()
[all …]
|
| H A D | SPIRVUtils.cpp | 62 MIB.addImm(convertCharsToWord(Str, i)); in addStringImm()
79 void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB) { in addNumImm() argument
84 MIB.addImm(Imm.getZExtValue()); in addNumImm()
90 MIB.addImm(LowBits).addImm(HighBits); in addNumImm()
100 addStringImm(Name, MIB); in buildOpName()
104 static void finishBuildOpDecorate(MachineInstrBuilder &MIB, in finishBuildOpDecorate() argument
108 addStringImm(StrImm, MIB); in finishBuildOpDecorate()
110 MIB.addImm(DecArg); in finishBuildOpDecorate()
116 auto MIB = MIRBuilder.buildInstr(SPIRV::OpDecorate) in buildOpDecorate() local
119 finishBuildOpDecorate(MIB, DecArgs, StrImm); in buildOpDecorate()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kCallLowering.cpp | 37 MachineInstrBuilder &MIB) in CallReturnHandler()
38 : M68kIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
44 MachineInstrBuilder &MIB; member
54 MachineInstrBuilder MIB) in M68kOutgoingArgHandler()
55 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB), in M68kOutgoingArgHandler()
61 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
89 MachineInstrBuilder MIB; member
118 MIRBuilder.insertInstr(MIB); in lowerReturn()
185 MIB.addDef(PhysReg, RegState::Implicit); in assignValueToReg()
228 *STI.getRegBankInfo(), *MIB, MIB->getDesc(), in lowerCall()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 83 MIB.setMF(MF); in setupMF()
1593 MIB); in emitTestBit()
1999 auto MIB = in selectVaStartDarwin() local
7296 [=](MachineInstrBuilder &MIB) { MIB.add(Base); }, in selectAddrModeUnscaled()
7353 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, in selectAddrModeIndexed()
7381 [=](MachineInstrBuilder &MIB) { MIB.add(LHS); }, in selectAddrModeIndexed()
7393 [=](MachineInstrBuilder &MIB) { MIB.add(Root); }, in selectAddrModeIndexed()
7394 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, in selectAddrModeIndexed()
7668 MIB.addImm( in renderFPImm16()
7677 MIB.addImm( in renderFPImm32()
[all …]
|
| H A D | AArch64CallLowering.cpp | 220 : IncomingArgHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
226 MachineInstrBuilder MIB; member
243 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB), IsTailCall(IsTailCall), in OutgoingArgHandler()
331 MachineInstrBuilder MIB; member
1081 MIB.add(Info.Callee); in lowerTailCall()
1085 MIB.addImm(0); in lowerTailCall()
1093 MIB.addRegMask(Mask); in lowerTailCall()
1202 MIB->getDesc(), MIB->getOperand(0), 0); in lowerTailCall()
1312 MIB.add(Info.Callee); in lowerCall()
1330 MIB.addRegMask(Mask); in lowerCall()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86CallLowering.cpp | 88 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB), in X86OutgoingValueHandler()
110 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
127 MachineInstrBuilder &MIB; member
175 MIRBuilder.insertInstr(MIB); in lowerReturn()
241 MachineInstrBuilder &MIB) in CallReturnHandler()
242 : X86IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
245 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
249 MachineInstrBuilder &MIB; member
368 MIB.addUse(X86::AL, RegState::Implicit); in lowerCall()
372 MIRBuilder.insertInstr(MIB); in lowerCall()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonOptAddrMode.cpp | 568 MachineInstrBuilder MIB; in changeLoad() local
575 MIB.add(OldMI->getOperand(0)); in changeLoad()
576 MIB.add(OldMI->getOperand(2)); in changeLoad()
577 MIB.add(OldMI->getOperand(3)); in changeLoad()
578 MIB.add(ImmOp); in changeLoad()
605 MIB.add(ImmOp); in changeLoad()
629 MachineInstrBuilder MIB; in changeStore() local
637 MIB.add(ImmOp); in changeStore()
656 MIB.add(OldMI->getOperand(0)); in changeStore()
657 MIB.add(ImmOp); in changeStore()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsSizeReduction.cpp | 714 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
717 MIB.add(MI->getOperand(0)); in ReplaceInstruction()
718 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
723 MIB.add(MI->getOperand(0)); in ReplaceInstruction()
724 MIB.add(MI->getOperand(1)); in ReplaceInstruction()
725 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
727 MIB.add(MI->getOperand(0)); in ReplaceInstruction()
728 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
729 MIB.add(MI->getOperand(1)); in ReplaceInstruction()
737 MIB.add(MI->getOperand(0)); in ReplaceInstruction()
[all …]
|