| /freebsd/contrib/llvm-project/lldb/include/lldb/Core/ |
| H A D | Opcode.h | 29 class Opcode {
41 Opcode() = default;
79 case Opcode::eType8:
81 case Opcode::eType16:
85 case Opcode::eType32:
87 case Opcode::eType64:
99 case Opcode::eType8:
101 case Opcode::eType16:
106 case Opcode::eType32:
120 case Opcode::eType8:
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 97 return Opcode == BPF::STB_imm || Opcode == BPF::STH_imm || in isST()
98 Opcode == BPF::STW_imm || Opcode == BPF::STD_imm; in isST()
102 return Opcode == BPF::STB32 || Opcode == BPF::STH32 || Opcode == BPF::STW32; in isSTX32()
106 return Opcode == BPF::STB || Opcode == BPF::STH || Opcode == BPF::STW || in isSTX64()
111 return Opcode == BPF::LDB32 || Opcode == BPF::LDH32 || Opcode == BPF::LDW32; in isLDX32()
115 return Opcode == BPF::LDB || Opcode == BPF::LDH || Opcode == BPF::LDW || in isLDX64()
120 return Opcode == BPF::LDBSX || Opcode == BPF::LDHSX || Opcode == BPF::LDWSX; in isLDSX()
124 return isLDX32(Opcode) || isLDX64(Opcode) || isLDSX(Opcode); in isLoadInst()
145 if (isLDX64(Opcode) || isLDSX(Opcode)) in checkADDrr()
149 else if (isSTX64(Opcode) || isSTX32(Opcode) || isST(Opcode)) in checkADDrr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 429 return isMIMG(Opcode) || isVSAMPLE(Opcode) || isVIMAGE(Opcode); in isImage()
437 return isMUBUF(Opcode) || isMTBUF(Opcode) || isImage(Opcode); in isVMEM()
566 bool isLDSDMA(uint16_t Opcode) { in isLDSDMA() argument
567 return isVALU(Opcode) && (isMUBUF(Opcode) || isFLAT(Opcode)); in isLDSDMA()
728 return get(Opcode).TSFlags & in isSpillOpcode()
931 switch (Opcode) { in getNonSoftWaitcntOpcode()
947 return Opcode; in getNonSoftWaitcntOpcode()
1422 int getVOPe64(uint16_t Opcode);
1425 int getVOPe32(uint16_t Opcode);
1428 int getSDWAOp(uint16_t Opcode);
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| H A D | R600InstrInfo.h | 84 bool isALUInstr(unsigned Opcode) const;
85 bool hasInstrModifiers(unsigned Opcode) const;
86 bool isLDSInstr(unsigned Opcode) const;
87 bool isLDSRetInstr(unsigned Opcode) const;
93 bool isTransOnly(unsigned Opcode) const;
95 bool isVectorOnly(unsigned Opcode) const;
97 bool isExport(unsigned Opcode) const;
99 bool usesVertexCache(unsigned Opcode) const;
101 bool usesTextureCache(unsigned Opcode) const;
158 bool isMov(unsigned Opcode) const;
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| /freebsd/contrib/llvm-project/lldb/source/Core/ |
| H A D | Opcode.cpp | 30 case Opcode::eType8: in Dump()
33 case Opcode::eType16: in Dump()
36 case Opcode::eType16_2: in Dump()
37 case Opcode::eType32: in Dump()
41 case Opcode::eType64: in Dump()
45 case Opcode::eTypeBytes: in Dump()
69 case Opcode::eType8: in GetDataByteOrder()
70 case Opcode::eType16: in GetDataByteOrder()
71 case Opcode::eType16_2: in GetDataByteOrder()
72 case Opcode::eType32: in GetDataByteOrder()
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| /freebsd/contrib/llvm-project/clang/lib/AST/Interp/ |
| H A D | Opcodes.td | 120 class Opcode {
168 def Ret : Opcode {
191 def Call : Opcode {
250 def Zero : Opcode {
264 def Null : Opcode {
344 def This : Opcode;
530 def Shl : Opcode {
535 def Shr : Opcode {
545 def Inv: Opcode {
563 def Neg: Opcode {
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/ |
| H A D | RISCVCustomBehaviour.cpp | 191 switch (Opcode) { in getEEWAndEMUL()
229 return Opcode == RISCV::VLM_V || Opcode == RISCV::VSM_V || in opcodeHasEEWAndEMULInfo()
230 Opcode == RISCV::VLE8_V || Opcode == RISCV::VSE8_V || in opcodeHasEEWAndEMULInfo()
231 Opcode == RISCV::VLE16_V || Opcode == RISCV::VSE16_V || in opcodeHasEEWAndEMULInfo()
232 Opcode == RISCV::VLE32_V || Opcode == RISCV::VSE32_V || in opcodeHasEEWAndEMULInfo()
233 Opcode == RISCV::VLE64_V || Opcode == RISCV::VSE64_V || in opcodeHasEEWAndEMULInfo()
234 Opcode == RISCV::VLSE8_V || Opcode == RISCV::VSSE8_V || in opcodeHasEEWAndEMULInfo()
235 Opcode == RISCV::VLSE16_V || Opcode == RISCV::VSSE16_V || in opcodeHasEEWAndEMULInfo()
236 Opcode == RISCV::VLSE32_V || Opcode == RISCV::VSSE32_V || in opcodeHasEEWAndEMULInfo()
237 Opcode == RISCV::VLSE64_V || Opcode == RISCV::VSSE64_V; in opcodeHasEEWAndEMULInfo()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | Instruction.h | 258 return Opcode >= TermOpsBegin && Opcode < TermOpsEnd;
262 return Opcode >= UnaryOpsBegin && Opcode < UnaryOpsEnd;
265 return Opcode >= BinaryOpsBegin && Opcode < BinaryOpsEnd;
269 return Opcode == UDiv || Opcode == SDiv || Opcode == URem || Opcode == SRem;
274 return Opcode >= Shl && Opcode <= AShr;
289 return Opcode == And || Opcode == Or || Opcode == Xor;
299 return Opcode >= CastOpsBegin && Opcode < CastOpsEnd;
304 return Opcode >= FuncletPadOpsBegin && Opcode < FuncletPadOpsEnd;
664 return Opcode == And || Opcode == Or || Opcode == Xor ||
665 Opcode == Add || Opcode == Mul;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVMakeCompressible.cpp | 98 static unsigned log2LdstWidth(unsigned Opcode) { in log2LdstWidth() argument
99 switch (Opcode) { in log2LdstWidth()
118 return 0x1f << log2LdstWidth(Opcode); in compressedLDSTOffsetMask()
146 const unsigned Opcode = MI.getOpcode(); in isCompressibleLoad() local
148 return Opcode == RISCV::LW || (!STI.is64Bit() && Opcode == RISCV::FLW) || in isCompressibleLoad()
149 Opcode == RISCV::LD || Opcode == RISCV::FLD; in isCompressibleLoad()
155 const unsigned Opcode = MI.getOpcode(); in isCompressibleStore() local
157 return Opcode == RISCV::SW || (!STI.is64Bit() && Opcode == RISCV::FSW) || in isCompressibleStore()
158 Opcode == RISCV::SD || Opcode == RISCV::FSD; in isCompressibleStore()
174 const unsigned Opcode = MI.getOpcode(); in getRegImmPairPreventingCompression() local
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| H A D | RISCVTargetTransformInfo.cpp | 158 switch (Opcode) { in getIntImmCostInst()
596 if (Opcode == Instruction::Load) { in getInterleavedMemoryOpCost()
642 if ((Opcode == Instruction::Load && in getGatherScatterOpCost()
644 (Opcode == Instruction::Store && in getGatherScatterOpCost()
964 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getArithmeticReductionCost()
1000 if (Opcode != Instruction::Add && Opcode != Instruction::FAdd) in getExtendedReductionCost()
1108 if ((Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) && in getCmpSelInstrCost()
1149 return Opcode == Instruction::PHI ? 0 : 1; in getCFInstrCost()
1160 if (Opcode != Instruction::ExtractElement && in getVectorInstrCost()
1161 Opcode != Instruction::InsertElement) in getVectorInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZTargetTransformInfo.cpp | 118 switch (Opcode) { in getIntImmCostInst()
449 Opcode == Instruction::SDiv || Opcode == Instruction::SRem; in getArithmeticInstrCost()
451 Opcode == Instruction::UDiv || Opcode == Instruction::URem; in getArithmeticInstrCost()
474 if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub || in getArithmeticInstrCost()
475 Opcode == Instruction::FMul || Opcode == Instruction::FDiv) in getArithmeticInstrCost()
533 if (Opcode == Instruction::Shl || Opcode == Instruction::LShr || in getArithmeticInstrCost()
556 if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub || in getArithmeticInstrCost()
557 Opcode == Instruction::FMul || Opcode == Instruction::FDiv) { in getArithmeticInstrCost()
760 if (Opcode == Instruction::ZExt || Opcode == Instruction::UIToFP) in getBoolVecToIntConversionCost()
861 if (Opcode == Instruction::ZExt || Opcode == Instruction::SExt) { in getCastInstrCost()
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| H A D | SystemZInstrInfo.cpp | 270 unsigned Opcode; in emitGRX32Move() local
751 if (Opcode == SystemZ::Return || Opcode == SystemZ::Return_XPLINK) { in PredicateInstruction()
857 unsigned Opcode; in copyPhysReg() local
939 switch (Opcode) { in interpretAndImmediate()
1070 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI); in foldMemoryOperandImpl()
1112 switch (Opcode) { in foldMemoryOperandImpl()
1137 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) { in foldMemoryOperandImpl()
1659 return Opcode; in getOpcodeForOffset()
1700 switch (Opcode) { in getLoadAndTest()
1755 switch (Opcode) { in getFusedCompare()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86AvoidStoreForwardingBlocks.cpp | 134 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm || in isXMMLoadOpcode()
135 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm || in isXMMLoadOpcode()
136 Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm || in isXMMLoadOpcode()
137 Opcode == X86::VMOVDQUrm || Opcode == X86::VMOVDQArm || in isXMMLoadOpcode()
144 return Opcode == X86::VMOVUPSYrm || Opcode == X86::VMOVAPSYrm || in isYMMLoadOpcode()
145 Opcode == X86::VMOVUPDYrm || Opcode == X86::VMOVAPDYrm || in isYMMLoadOpcode()
146 Opcode == X86::VMOVDQUYrm || Opcode == X86::VMOVDQAYrm || in isYMMLoadOpcode()
154 return isXMMLoadOpcode(Opcode) || isYMMLoadOpcode(Opcode); in isPotentialBlockedMemCpyLd()
212 Opcode == X86::MOV32mr || Opcode == X86::MOV32mi || in isPotentialBlockingStoreInst()
213 Opcode == X86::MOV16mr || Opcode == X86::MOV16mi || in isPotentialBlockingStoreInst()
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| /freebsd/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/ |
| H A D | DWARFExpression.cpp | 116 return Descriptions[Opcode]; in getDescImpl()
147 Desc = getOpDesc(Opcode); in extract()
267 if (Opcode == DW_OP_bregx || Opcode == DW_OP_regx || in prettyPrintRegisterOp()
270 else if (Opcode >= DW_OP_breg0 && Opcode < DW_OP_bregx) in prettyPrintRegisterOp()
277 if ((Opcode >= DW_OP_breg0 && Opcode <= DW_OP_breg31) || in prettyPrintRegisterOp()
278 Opcode == DW_OP_bregx) in prettyPrintRegisterOp()
309 if ((Opcode >= DW_OP_breg0 && Opcode <= DW_OP_breg31) || in print()
310 (Opcode >= DW_OP_reg0 && Opcode <= DW_OP_reg31) || in print()
311 Opcode == DW_OP_bregx || Opcode == DW_OP_regx || in print()
446 switch (Opcode) { in printCompactDWARFExpr()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegacyLegalizerInfo.h | 85 unsigned Opcode; member
89 InstrAspect(unsigned Opcode, LLT Type) : Opcode(Opcode), Type(Type) {} in InstrAspect()
90 InstrAspect(unsigned Opcode, unsigned Idx, LLT Type) in InstrAspect()
91 : Opcode(Opcode), Idx(Idx), Type(Type) {} in InstrAspect()
94 return Opcode == RHS.Opcode && Idx == RHS.Idx && Type == RHS.Type;
183 const unsigned OpcodeIdx = Opcode - FirstOp; in setLegalizeScalarToDifferentSizeStrategy()
194 const unsigned OpcodeIdx = Opcode - FirstOp; in setLegalizeVectorElementToDifferentSizeStrategy()
313 const unsigned OpcodeIdx = Opcode - FirstOp; in setScalarAction()
320 const unsigned OpcodeIdx = Opcode - FirstOp; in setPointerAction()
336 unsigned OpcodeIdx = Opcode - FirstOp; in setScalarInVectorAction()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetOpcodes.h | 30 inline bool isPreISelGenericOpcode(unsigned Opcode) { in isPreISelGenericOpcode() argument
31 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START && in isPreISelGenericOpcode()
32 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isPreISelGenericOpcode()
36 inline bool isTargetSpecificOpcode(unsigned Opcode) { in isTargetSpecificOpcode() argument
37 return Opcode > TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isTargetSpecificOpcode()
42 inline bool isPreISelGenericOptimizationHint(unsigned Opcode) { in isPreISelGenericOptimizationHint() argument
43 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START && in isPreISelGenericOptimizationHint()
44 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END; in isPreISelGenericOptimizationHint()
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| H A D | ISDOpcodes.h | 1398 inline bool isBitwiseLogicOp(unsigned Opcode) { in isBitwiseLogicOp() argument
1399 return Opcode == ISD::AND || Opcode == ISD::OR || Opcode == ISD::XOR; in isBitwiseLogicOp()
1407 bool isVPOpcode(unsigned Opcode);
1410 bool isVPBinaryOp(unsigned Opcode);
1413 bool isVPReduction(unsigned Opcode);
1425 unsigned getVPForBaseOpcode(unsigned Opcode);
1577 inline bool isExtOpcode(unsigned Opcode) { in isExtOpcode() argument
1578 return Opcode == ISD::ANY_EXTEND || Opcode == ISD::ZERO_EXTEND || in isExtOpcode()
1579 Opcode == ISD::SIGN_EXTEND; in isExtOpcode()
1582 inline bool isExtVecInRegOpcode(unsigned Opcode) { in isExtVecInRegOpcode() argument
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerInfo.cpp | 80 OS << "Opcode=" << Opcode << ", Tys={"; in print()
269 assert(Opcode >= FirstOp && Opcode <= LastOp && "Unsupported opcode"); in getOpcodeIdxForOpcode()
270 return Opcode - FirstOp; in getOpcodeIdxForOpcode()
274 unsigned OpcodeIdx = getOpcodeIdxForOpcode(Opcode); in getActionDefinitionsIdx()
382 for (unsigned Opcode = FirstOp; Opcode <= LastOp; ++Opcode) { in verify() local
383 const MCInstrDesc &MCID = MII.get(Opcode); in verify()
398 LLVM_DEBUG(dbgs() << MII.getName(Opcode) << " (opcode " << Opcode in verify()
405 FailedOpcodes.push_back(Opcode); in verify()
407 FailedOpcodes.push_back(Opcode); in verify()
411 for (unsigned Opcode : FailedOpcodes) in verify() local
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| /freebsd/contrib/llvm-project/llvm/tools/llvm-readobj/ |
| H A D | ARMEHABIPrinter.h | 99 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_00xxxxxx() local
105 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_01xxxxxx() local
124 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011101() local
129 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011111() local
134 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_1001nnnn() local
135 SW.startLine() << format("0x%02X ; vsp = r%u\n", Opcode, (Opcode & 0x0f)); in Decode_1001nnnn()
139 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10100nnn() local
146 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10101nnn() local
153 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110000() local
169 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110010_uleb128() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMUnwindOpAsm.h | 72 void EmitInt8(unsigned Opcode) { in EmitInt8() argument
73 Ops.push_back(Opcode & 0xff); in EmitInt8()
77 void EmitInt16(unsigned Opcode) { in EmitInt16() argument
78 Ops.push_back((Opcode >> 8) & 0xff); in EmitInt16()
79 Ops.push_back(Opcode & 0xff); in EmitInt16()
83 void emitBytes(const uint8_t *Opcode, size_t Size) { in emitBytes() argument
84 Ops.insert(Ops.end(), Opcode, Opcode + Size); in emitBytes()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetTransformInfo.cpp | 184 assert(Opcode == Instruction::Load || Opcode == Instruction::Store); in getMemoryOpCost()
189 if (Opcode == Instruction::Store) in getMemoryOpCost()
190 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, in getMemoryOpCost()
236 HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, in getMaskedMemoryOpCost() argument
252 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, in getGatherScatterOpCost() argument
254 return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask, in getGatherScatterOpCost()
280 if (Opcode == Instruction::FCmp) in getCmpSelInstrCost()
287 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost() argument
293 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, in getArithmeticInstrCost()
340 if (Opcode == Instruction::InsertElement) { in getVectorInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo.cpp | 191 switch (Opcode) { in getOppositeBranchOpc()
405 unsigned Opcode = 0; in storeRegToStackSlot() local
413 Opcode = CSKY::FST_S; in storeRegToStackSlot()
415 Opcode = CSKY::FST_D; in storeRegToStackSlot()
449 unsigned Opcode = 0; in loadRegFromStackSlot() local
452 Opcode = CSKY::LD32W; in loadRegFromStackSlot()
457 Opcode = CSKY::FLD_S; in loadRegFromStackSlot()
459 Opcode = CSKY::FLD_D; in loadRegFromStackSlot()
521 unsigned Opcode = 0; in copyPhysReg() local
525 Opcode = CSKY::FMOV_S; in copyPhysReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCA/ |
| H A D | AMDGPUCustomBehaviour.cpp | 72 unsigned Opcode = Inst.getOpcode(); in checkCustomHazard() local
78 switch (Opcode) { in checkCustomHazard()
182 unsigned Opcode = Inst.getOpcode(); in computeWaitCnt() local
184 switch (Opcode) { in computeWaitCnt()
204 switch (Opcode) { in computeWaitCnt()
249 unsigned Opcode = Inst->getOpcode(); in generateWaitCntInfo() local
250 const MCInstrDesc &MCID = MCII.get(Opcode); in generateWaitCntInfo()
291 switch (Opcode) { in generateWaitCntInfo()
325 bool AMDGPUCustomBehaviour::isGWS(uint16_t Opcode) const { in isGWS()
326 const MCInstrDesc &MCID = MCII.get(Opcode); in isGWS()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 222 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; in getMemoryOpOffset()
226 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 || in getMemoryOpOffset()
227 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 || in getMemoryOpOffset()
229 Opcode == ARM::LDRi12 || Opcode == ARM::STRi12) in getMemoryOpOffset()
233 if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi || in getMemoryOpOffset()
234 Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) in getMemoryOpOffset()
783 Opcode = getLoadStoreMultipleOpcode(Opcode, Mode); in CreateLoadStoreMulti()
963 assert(isi32Store(Opcode) || Opcode == ARM::VSTRS || Opcode == ARM::VSTRD); in MergeOpsUpdate()
992 if (!isi32Load(Opcode) && !isi32Store(Opcode)) in mayCombineMisaligned()
1481 if (isi32Load(Opcode) || isi32Store(Opcode)) in MergeBaseUpdateLoadStore()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetTransformInfo.cpp | 246 switch (Opcode) { in getIntImmCostInst()
571 int ISD = TLI->InstructionOpcodeToISD(Opcode); in vectorCostAdjustmentFactor()
602 Opcode, Ty, CostKind, Op1Info, Op2Info); in getArithmeticInstrCost()
632 return Opcode == Instruction::PHI ? 0 : 1; in getCFInstrCost()
663 vectorCostAdjustmentFactor(Opcode, ValTy, nullptr); in getCmpSelInstrCost()
681 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getVectorInstrCost()
771 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && in getMemoryOpCost()
835 if (Src->isVectorTy() && Opcode == Instruction::Store) in getMemoryOpCost()
1007 if (Opcode != Instruction::Load && Opcode != Instruction::Store) in hasActiveVectorLength()
1045 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && in getVPMemoryOpCost()
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