/freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
H A D | CGNonTrivialStruct.cpp | 680 Addrs[SrcIdx] = getAddrWithOffset(Addrs[SrcIdx], CurStructOffset, FD); in visitARCStrong() 690 Addrs[SrcIdx] = getAddrWithOffset(Addrs[SrcIdx], CurStructOffset, FD); in visitARCWeak() 697 Addrs[SrcIdx] = getAddrWithOffset(Addrs[SrcIdx], Offset); in callSpecialFunction() 710 Addrs[SrcIdx] = getAddrWithOffset(Addrs[SrcIdx], CurStructOffset, FD); in visitARCStrong() 722 Addrs[SrcIdx] = getAddrWithOffset(Addrs[SrcIdx], CurStructOffset, FD); in visitARCWeak() 729 Addrs[SrcIdx] = getAddrWithOffset(Addrs[SrcIdx], Offset); in callSpecialFunction() 742 Addrs[SrcIdx] = getAddrWithOffset(Addrs[SrcIdx], CurStructOffset, FD); in visitARCStrong() 752 Addrs[SrcIdx] = getAddrWithOffset(Addrs[SrcIdx], CurStructOffset, FD); in visitARCWeak() 759 Addrs[SrcIdx] = getAddrWithOffset(Addrs[SrcIdx], Offset); in callSpecialFunction() 773 Addrs[SrcIdx] = getAddrWithOffset(Addrs[SrcIdx], CurStructOffset, FD); in visitARCStrong() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | RegisterCoalescer.h | 42 unsigned SrcIdx = 0; variable 106 unsigned getSrcIdx() const { return SrcIdx; } in getSrcIdx()
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H A D | TwoAddressInstructionPass.cpp | 1249 Register regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform() 1283 regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform() 1443 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { in collectTiedOperands() local 1448 MachineOperand &SrcMO = MI->getOperand(SrcIdx); in collectTiedOperands() 1492 unsigned SrcIdx = TP.first; in processTiedPairs() local 1500 RegB = MI->getOperand(SrcIdx).getReg(); in processTiedPairs() 1501 SubRegB = MI->getOperand(SrcIdx).getSubReg(); in processTiedPairs() 1576 MachineOperand &MO = MI->getOperand(SrcIdx); in processTiedPairs() 1677 unsigned SrcIdx = TO.second[0].first; in processStatepoint() local 1739 if (MI->getOperand(SrcIdx).isKill()) in processStatepoint() [all …]
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H A D | RegisterCoalescer.cpp | 454 SrcIdx = DstIdx = 0; in setRegisters() 507 SrcIdx = DstSub; in setRegisters() 524 if (DstIdx && !SrcIdx) { in setRegisters() 526 std::swap(SrcIdx, DstIdx); in setRegisters() 544 std::swap(SrcIdx, DstIdx); in flip() 583 return TRI.composeSubRegIndices(SrcIdx, SrcSub) == in isCoalescable() 1338 if (SrcIdx && DstIdx) in reMaterializeTrivialDef() 1386 assert(SrcIdx == 0 && CP.isFlipped() in reMaterializeTrivialDef() 1983 unsigned SrcIdx = CP.getSrcIdx(); in joinCopy() local 1986 std::swap(SrcIdx, DstIdx); in joinCopy() [all …]
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H A D | PeepholeOptimizer.cpp | 1919 unsigned SrcIdx = Def->getNumOperands(); in getNextSourceFromBitcast() local 1920 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; in getNextSourceFromBitcast() 1929 if (SrcIdx != EndOpIdx) in getNextSourceFromBitcast() 1932 SrcIdx = OpIdx; in getNextSourceFromBitcast() 1937 if (SrcIdx >= Def->getNumOperands()) in getNextSourceFromBitcast() 1947 const MachineOperand &Src = Def->getOperand(SrcIdx); in getNextSourceFromBitcast()
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H A D | TargetRegisterInfo.cpp | 393 unsigned SrcIdx, DefIdx; in shareSameRegisterFile() local 396 SrcIdx, DefIdx) != nullptr; in shareSameRegisterFile()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ExpandPseudoInsts.cpp | 487 unsigned PredIdx, DOPIdx, SrcIdx, Src2Idx; in expand_DestructiveOp() local 494 std::tie(PredIdx, DOPIdx, SrcIdx) = std::make_tuple(1, 3, 2); in expand_DestructiveOp() 501 std::tie(PredIdx, DOPIdx, SrcIdx) = std::make_tuple(1, 2, 3); in expand_DestructiveOp() 504 std::tie(PredIdx, DOPIdx, SrcIdx) = std::make_tuple(2, 3, 3); in expand_DestructiveOp() 507 std::tie(PredIdx, DOPIdx, SrcIdx, Src2Idx) = std::make_tuple(1, 2, 3, 4); in expand_DestructiveOp() 528 DOPRegIsUnique = DstReg != MI.getOperand(SrcIdx).getReg(); in expand_DestructiveOp() 534 MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg(); in expand_DestructiveOp() 543 (MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg() && in expand_DestructiveOp() 642 .add(MI.getOperand(SrcIdx)); in expand_DestructiveOp() 650 .add(MI.getOperand(SrcIdx)); in expand_DestructiveOp() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86MCInstLower.cpp | 1693 unsigned SrcIdx = 1; in addConstantComments() local 1696 ++SrcIdx; in addConstantComments() 1699 ++SrcIdx; in addConstantComments() 1703 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) { in addConstantComments() 1708 OutStreamer.AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask)); in addConstantComments() 1766 unsigned SrcIdx = 1; in addConstantComments() local 1769 ++SrcIdx; in addConstantComments() 1772 ++SrcIdx; in addConstantComments() 1776 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) { in addConstantComments() 1781 OutStreamer.AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask)); in addConstantComments()
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H A D | X86InstrInfo.cpp | 2438 unsigned SrcIdx = (Imm >> 6) & 3; in commuteInstructionImpl() local 2442 if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 && in commuteInstructionImpl() 7200 unsigned SrcIdx = (Imm >> 6) & 3; in foldMemoryOperandCustom() local 7207 int PtrOffset = SrcIdx * 4; in foldMemoryOperandCustom()
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H A D | X86ISelLowering.cpp | 5554 unsigned SrcIdx = M / Size; in getTargetShuffleAndZeroables() local 5594 if (IsSrcConstant[SrcIdx]) { in getTargetShuffleAndZeroables() 5595 if (UndefSrcElts[SrcIdx][M]) in getTargetShuffleAndZeroables() 5597 else if (SrcEltBits[SrcIdx][M] == 0) in getTargetShuffleAndZeroables() 11784 int SrcIdx = i + Offset; in lowerShuffleAsSpecificZeroOrAnyExtend() local 11785 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1; in lowerShuffleAsSpecificZeroOrAnyExtend() 40422 if (KnownUndef1[SrcIdx] || KnownZero1[SrcIdx]) { in combineTargetShuffle() 40429 int M = TargetMask1[SrcIdx]; in combineTargetShuffle() 41554 unsigned SrcIdx = (LoMask & 0x2) >> 1; in SimplifyDemandedVectorEltsForTargetNode() local 47328 if (UndefElts[SrcIdx]) { in combineVectorPack() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | Utils.cpp | 981 for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) { in ConstantFoldCTLZ() local 982 if (auto MaybeFold = tryFoldScalar(BV->getSourceReg(SrcIdx))) { in ConstantFoldCTLZ() 1357 for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) { in isConstantOrConstantVector() local 1358 if (getIConstantVRegValWithLookThrough(BV->getSourceReg(SrcIdx), MRI) || in isConstantOrConstantVector() 1359 getOpcodeDef<GImplicitDef>(BV->getSourceReg(SrcIdx), MRI)) in isConstantOrConstantVector()
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H A D | CombinerHelper.cpp | 2019 unsigned SrcIdx = MI.getNumOperands() - 1; in matchCombineUnmergeConstant() local 2020 Register SrcReg = MI.getOperand(SrcIdx).getReg(); in matchCombineUnmergeConstant() 2034 for (unsigned Idx = 0; Idx != SrcIdx; ++Idx) { in matchCombineUnmergeConstant() 2060 unsigned SrcIdx = MI.getNumOperands() - 1; in matchCombineUnmergeUndef() local 2061 Register SrcReg = MI.getOperand(SrcIdx).getReg(); in matchCombineUnmergeUndef()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.h | 111 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const; 309 MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
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H A D | R600InstrInfo.cpp | 233 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const { in getSelIdx() 249 if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) { in getSelIdx() 292 int SrcIdx = getOperandIdx(MI.getOpcode(), Op[0]); in getSrcs() local 293 if (SrcIdx < 0) in getSrcs() 295 MachineOperand &MO = MI.getOperand(SrcIdx); in getSrcs() 1374 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx, in getFlagOp() argument 1396 switch (SrcIdx) { in getFlagOp() 1413 switch (SrcIdx) { in getFlagOp()
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H A D | R600ISelLowering.h | 110 bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
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H A D | AMDGPUInstCombineIntrinsic.cpp | 1287 for (unsigned SrcIdx = 0; SrcIdx < 4; ++SrcIdx) { in simplifyAMDGCNMemoryIntrinsicDemanded() local 1288 const unsigned Bit = 1 << SrcIdx; in simplifyAMDGCNMemoryIntrinsicDemanded()
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H A D | SIFoldOperands.cpp | 249 unsigned SrcIdx = ~0; in tryFoldImmWithOpSel() local 252 SrcIdx = 0; in tryFoldImmWithOpSel() 255 SrcIdx = 1; in tryFoldImmWithOpSel() 258 SrcIdx = 2; in tryFoldImmWithOpSel() 333 if (SrcIdx == 1 && (IsUAdd || IsUSub)) { in tryFoldImmWithOpSel()
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H A D | R600ISelLowering.cpp | 1945 bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx, in FoldOperand() argument
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | InferAddressSpaces.cpp | 1267 int SrcIdx = U.getOperandNo(); in rewriteWithNewAddressSpaces() local 1268 int OtherIdx = (SrcIdx == 0) ? 1 : 0; in rewriteWithNewAddressSpaces() 1274 Cmp->setOperand(SrcIdx, NewV); in rewriteWithNewAddressSpaces() 1282 Cmp->setOperand(SrcIdx, NewV); in rewriteWithNewAddressSpaces()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | LegalizationArtifactCombiner.h | 671 for (unsigned SrcIdx = StartSrcIdx; SrcIdx < StartSrcIdx + NumSrcsUsed; in findValueFromBuildVector() local 672 ++SrcIdx) in findValueFromBuildVector() 673 NewSrcs.push_back(BV.getReg(SrcIdx)); in findValueFromBuildVector()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineVectorOps.cpp | 542 int SrcIdx = in visitExtractElementInst() local 548 if (SrcIdx < 0) in visitExtractElementInst() 550 if (SrcIdx < (int)LHSWidth) in visitExtractElementInst() 553 SrcIdx -= LHSWidth; in visitExtractElementInst() 558 Src, ConstantInt::get(Int64Ty, SrcIdx, false)); in visitExtractElementInst()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 4181 if (SrcIdx == -1) in validateLdsDirect() 4183 const auto &Src = Inst.getOperand(SrcIdx); in validateLdsDirect() 6783 int SrcIdx = 0; in cvtExp() local 6790 assert(SrcIdx < 4); in cvtExp() 6791 OperandIdx[SrcIdx] = Inst.size(); in cvtExp() 6793 ++SrcIdx; in cvtExp() 6798 assert(SrcIdx < 4); in cvtExp() 6799 OperandIdx[SrcIdx] = Inst.size(); in cvtExp() 6801 ++SrcIdx; in cvtExp() 6817 assert(SrcIdx == 4); in cvtExp() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/ |
H A D | InstrRefBasedImpl.cpp | 2093 LocIdx SrcIdx = MTracker->getSpillMLoc(SpillID); in transferSpillOrRestoreInst() local 2094 auto ReadValue = MTracker->readMLoc(SrcIdx); in transferSpillOrRestoreInst()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 862 SmallVectorImpl<int> &SrcIdx) { in buildHvxVectorReg() argument 866 SrcIdx.push_back(-1); in buildHvxVectorReg() 881 SrcIdx.push_back(I); in buildHvxVectorReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 4690 int SrcIdx = Mask[DstIdx]; in lowerShuffleViaVRegSplitting() local 4691 if (SrcIdx < 0 || (unsigned)SrcIdx >= 2 * NumElts) in lowerShuffleViaVRegSplitting() 4693 int SrcVecIdx = SrcIdx / ElemsPerVReg; in lowerShuffleViaVRegSplitting() 4694 int SrcSubIdx = SrcIdx % ElemsPerVReg; in lowerShuffleViaVRegSplitting()
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