/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 74 unsigned Lane, const TargetRegisterClass *TRC); 97 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC); 133 const TargetRegisterClass *TRC) { in usesRegClass() argument 139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass() 141 return TRC->contains(Reg); in usesRegClass() 269 const TargetRegisterClass *TRC = in optimizeSDPattern() local 271 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern() 432 const TargetRegisterClass *TRC) { in createExtractSubreg() argument 433 Register Out = MRI->createVirtualRegister(TRC); in createExtractSubreg()
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H A D | ARMLoadStoreOptimizer.cpp | 2428 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); in RescheduleOps() local 2429 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps() 2430 MRI->constrainRegClass(SecondReg, TRC); in RescheduleOps() 3023 const TargetRegisterClass *TRC = TII->getRegClass(MCID, BaseOp, TRI, *MF); in AdjustBaseAndOffset() local 3024 MRI.constrainRegClass(NewBaseReg, TRC); in AdjustBaseAndOffset() 3080 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); in createPostIncLoadStore() local 3081 MRI.constrainRegClass(NewReg, TRC); in createPostIncLoadStore() 3083 TRC = TII->getRegClass(MCID, 2, TRI, *MF); in createPostIncLoadStore() 3084 MRI.constrainRegClass(MI->getOperand(1).getReg(), TRC); in createPostIncLoadStore()
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H A D | ARMISelLowering.cpp | 11034 VReg2 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() 11139 NewVReg6 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() 11171 VReg2 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() 11461 const TargetRegisterClass *TRC = nullptr; in EmitStructByval() local 11569 Register varEnd = MRI.createVirtualRegister(TRC); in EmitStructByval() 11611 Register varLoop = MRI.createVirtualRegister(TRC); in EmitStructByval() 11612 Register varPhi = MRI.createVirtualRegister(TRC); in EmitStructByval() 11613 Register srcLoop = MRI.createVirtualRegister(TRC); in EmitStructByval() 11614 Register srcPhi = MRI.createVirtualRegister(TRC); in EmitStructByval() 11615 Register destLoop = MRI.createVirtualRegister(TRC); in EmitStructByval() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
H A D | M68kRegisterInfo.cpp | 107 const TargetRegisterClass &TRC) const { in getRegisterOrder() 108 for (unsigned i = 0; i < TRC.getNumRegs(); ++i) { in getRegisterOrder() 109 if (regsOverlap(Reg, TRC.getRegister(i))) { in getRegisterOrder()
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H A D | M68kRegisterInfo.h | 77 int getRegisterOrder(unsigned Reg, const TargetRegisterClass &TRC) const;
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/freebsd/usr.sbin/lpr/lpd/ |
H A D | printjob.c | 1488 #define TRC(q) (((q)-' ')&0177) macro 1502 d = dropit(c = TRC(cc = *sp++)); in scan_out() 1527 case TRC('_'): in dropit() 1528 case TRC(';'): in dropit() 1529 case TRC(','): in dropit() 1530 case TRC('g'): in dropit() 1531 case TRC('j'): in dropit() 1532 case TRC('p'): in dropit() 1533 case TRC('q'): in dropit() 1534 case TRC('y'): in dropit()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 499 const TargetRegisterClass *TRC = in EmitSubregNode() local 518 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode() 524 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode() 538 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode() 655 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local 657 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); in EmitRegSequence()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineRegisterInfo.cpp | 500 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg() local 501 return TRC.getLaneMask(); in getMaxLaneMaskForVReg()
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H A D | LiveDebugVariables.cpp | 1542 const TargetRegisterClass *TRC = MRI.getRegClass(VirtReg); in rewriteLocations() local 1543 bool Success = TII.getStackSlotRange(TRC, Loc.getSubReg(), SpillSize, in rewriteLocations() 1854 const TargetRegisterClass *TRC = MRI.getRegClass(Reg); in emitDebugValues() local 1857 unsigned regSizeInBits = TRI->getRegSizeInBits(*TRC); in emitDebugValues() 1865 TII->getStackSlotRange(TRC, SubReg, SpillSize, SpillOffset, *MF); in emitDebugValues()
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H A D | RegAllocPBQP.cpp | 617 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph() local 625 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF); in initializeGraph()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyAsmPrinter.cpp | 63 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); in getRegType() local 66 if (TRI->isTypeLegalForClass(*TRC, T)) in getRegType()
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/freebsd/contrib/llvm-project/clang/include/clang/AST/ |
H A D | ASTNodeTraverser.h | 440 if (const Expr *TRC = D->getTrailingRequiresClause()) in VisitFunctionDecl() local 441 Visit(TRC); in VisitFunctionDecl()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86AvoidStoreForwardingBlocks.cpp | 557 const auto *TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI, in getRegSizeInBytes() local 559 return TRI->getRegSizeInBits(*TRC) / 8; in getRegSizeInBytes()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.h | 1378 const TargetRegisterClass &TRC, in isOfRegClass() argument 1382 return RC == &TRC; in isOfRegClass() 1384 return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg); in isOfRegClass()
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/freebsd/contrib/llvm-project/clang/lib/Sema/ |
H A D | SemaTemplateVariadic.cpp | 976 if (Expr *TRC = D.getTrailingRequiresClause()) in containsUnexpandedParameterPacks() local 977 if (TRC->containsUnexpandedParameterPack()) in containsUnexpandedParameterPacks()
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H A D | SemaLambda.cpp | 1457 if (Expr *TRC = Method->getTrailingRequiresClause()) { in ActOnStartOfLambdaDefinition() local 1480 Diag(TRC->getBeginLoc(), diag::err_constrained_non_templated_function); in ActOnStartOfLambdaDefinition()
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H A D | SemaLookup.cpp | 5495 TypoDiagnosticGenerator TDG, TypoRecoveryCallback TRC, CorrectTypoKind Mode, in CorrectTypoDelayed() argument 5522 return createDelayedTypo(std::move(Consumer), std::move(TDG), std::move(TRC), in CorrectTypoDelayed() 5860 TypoRecoveryCallback TRC, in createDelayedTypo() argument 5867 State.RecoveryHandler = std::move(TRC); in createDelayedTypo()
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/freebsd/contrib/llvm-project/clang/include/clang/Sema/ |
H A D | DeclSpec.h | 2548 void setTrailingRequiresClause(Expr *TRC) { in setTrailingRequiresClause() argument 2549 TrailingRequiresClause = TRC; in setTrailingRequiresClause() 2551 SetRangeEnd(TRC->getEndLoc()); in setTrailingRequiresClause()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.cpp | 4116 const TargetRegisterClass *TRC = ::getRegClass(MI, Reg); in isHForm() local 4117 return TRC == &AArch64::FPR16RegClass || in isHForm() 4118 TRC == &AArch64::FPR16_loRegClass; in isHForm() 4131 return TRC == &AArch64::FPR128RegClass || in isQForm() 4132 TRC == &AArch64::FPR128_loRegClass; in isQForm() 4176 return TRC == &AArch64::FPR128RegClass || in isFpOrNEON() 4177 TRC == &AArch64::FPR128_loRegClass || in isFpOrNEON() 4178 TRC == &AArch64::FPR64RegClass || in isFpOrNEON() 4179 TRC == &AArch64::FPR64_loRegClass || in isFpOrNEON() 4180 TRC == &AArch64::FPR32RegClass || TRC == &AArch64::FPR16RegClass || in isFpOrNEON() [all …]
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | MachineIRBuilder.h | 80 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} in DstOp() argument
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/freebsd/contrib/llvm-project/clang/lib/AST/ |
H A D | DeclTemplate.cpp | 274 if (const Expr *TRC = FD->getTrailingRequiresClause()) in getAssociatedConstraints() local 275 AC.push_back(TRC); in getAssociatedConstraints()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/ |
H A D | InstrRefBasedImpl.cpp | 1529 const TargetRegisterClass *TRC = nullptr; in getValueForInstrRef() local 1532 TRC = TRCI; in getValueForInstrRef() 1533 assert(TRC && "Couldn't find target register class?"); in getValueForInstrRef() 1537 unsigned MainRegSize = TRI->getRegSizeInBits(*TRC); in getValueForInstrRef()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.cpp | 2102 const TargetRegisterClass *TRC; in createVR() local 2104 TRC = &Hexagon::PredRegsRegClass; in createVR() 2106 TRC = &Hexagon::IntRegsRegClass; in createVR() 2108 TRC = &Hexagon::DoubleRegsRegClass; in createVR() 2113 Register NewReg = MRI.createVirtualRegister(TRC); in createVR()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCMIPeephole.cpp | 1152 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 in simplifyCode() local 1155 MRI->setRegClass(DominatorReg, TRC); in simplifyCode()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 1794 const TargetRegisterClass *TRC = in SelectInlineAsmMemoryOperand() local 1797 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), DL, MVT::i32); in SelectInlineAsmMemoryOperand()
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