/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86ShuffleDecode.cpp | 479 unsigned VecSize = NumElts * ScalarBits; in DecodeVPERMILPMask() local 480 unsigned NumLanes = VecSize / 128; in DecodeVPERMILPMask() 482 assert((VecSize == 128 || VecSize == 256 || VecSize == 512) && in DecodeVPERMILPMask() 501 unsigned VecSize = NumElts * ScalarBits; in DecodeVPERMIL2PMask() local 502 unsigned NumLanes = VecSize / 128; in DecodeVPERMIL2PMask() 504 assert((VecSize == 128 || VecSize == 256) && "Unexpected vector size"); in DecodeVPERMIL2PMask()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonVExtract.cpp | 161 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8; in runOnMachineFunction() local 171 SR == 0 ? 0 : VecSize/2); in runOnMachineFunction()
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H A D | HexagonPatternsHVX.td | 96 int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass); 97 assert(isPowerOf2_32(VecSize)); 98 if ((uint32_t(V) & (uint32_t(VecSize)-1)) != 0) 100 int32_t L = Log2_32(VecSize);
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.cpp | 1401 if (VecSize <= 32) // 4 bytes in getIndirectGPRIDXPseudo() 1429 if (VecSize <= 32) // 4 bytes in getIndirectGPRIDXPseudo() 1431 if (VecSize <= 64) // 8 bytes in getIndirectGPRIDXPseudo() 1433 if (VecSize <= 96) // 12 bytes in getIndirectGPRIDXPseudo() 1458 if (VecSize <= 32) // 4 bytes in getIndirectVGPRWriteMovRelPseudoOpc() 1460 if (VecSize <= 64) // 8 bytes in getIndirectVGPRWriteMovRelPseudoOpc() 1462 if (VecSize <= 96) // 12 bytes in getIndirectVGPRWriteMovRelPseudoOpc() 1487 if (VecSize <= 32) // 4 bytes in getIndirectSGPRWriteMovRelPseudo32() 1489 if (VecSize <= 64) // 8 bytes in getIndirectSGPRWriteMovRelPseudo32() 1491 if (VecSize <= 96) // 12 bytes in getIndirectSGPRWriteMovRelPseudo32() [all …]
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H A D | AMDGPUISelDAGToDAG.cpp | 2951 unsigned VecSize = Src.getValueSizeInBits(); in SelectVOP3PMods() local 2955 if (Lo.getValueSizeInBits() > VecSize) { in SelectVOP3PMods() 2957 (VecSize > 32) ? AMDGPU::sub0_sub1 : AMDGPU::sub0, SDLoc(In), in SelectVOP3PMods() 2958 MVT::getIntegerVT(VecSize), Lo); in SelectVOP3PMods() 2961 if (Hi.getValueSizeInBits() > VecSize) { in SelectVOP3PMods() 2964 MVT::getIntegerVT(VecSize), Hi); in SelectVOP3PMods() 2967 assert(Lo.getValueSizeInBits() <= VecSize && in SelectVOP3PMods() 2968 Hi.getValueSizeInBits() <= VecSize); in SelectVOP3PMods() 2974 if (VecSize == 32 || VecSize == Lo.getValueSizeInBits()) { in SelectVOP3PMods() 2977 assert(Lo.getValueSizeInBits() == 32 && VecSize == 64); in SelectVOP3PMods() [all …]
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H A D | SIInstrInfo.h | 308 const MCInstrDesc &getIndirectRegWriteMovRelPseudo(unsigned VecSize, 312 const MCInstrDesc &getIndirectGPRIDXPseudo(unsigned VecSize,
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H A D | SIISelLowering.cpp | 6776 unsigned VecSize = VecVT.getSizeInBits(); in lowerINSERT_VECTOR_ELT() local 6820 MVT IntVT = MVT::getIntegerVT(VecSize); in lowerINSERT_VECTOR_ELT() 6868 if (VecSize == 128 || VecSize == 256 || VecSize == 512) { in lowerEXTRACT_VECTOR_ELT() 6873 if (VecSize == 128) { in lowerEXTRACT_VECTOR_ELT() 6881 } else if (VecSize == 256) { in lowerEXTRACT_VECTOR_ELT() 6894 assert(VecSize == 512); in lowerEXTRACT_VECTOR_ELT() 6920 assert(VecSize <= 64); in lowerEXTRACT_VECTOR_ELT() 6922 MVT IntVT = MVT::getIntegerVT(VecSize); in lowerEXTRACT_VECTOR_ELT() 13030 unsigned VecSize = EltSize * NumElem; in shouldExpandVectorDynExt() local 13033 if (VecSize <= 64 && EltSize < 32) in shouldExpandVectorDynExt() [all …]
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H A D | AMDGPURegisterBankInfo.cpp | 4284 unsigned VecSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); in getInstrMapping() local 4290 OpdsMapping[0] = AMDGPU::getValueMapping(OutputBankID, VecSize); in getInstrMapping() 4291 OpdsMapping[1] = AMDGPU::getValueMapping(OutputBankID, VecSize); in getInstrMapping()
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H A D | SIInstructions.td | 2391 multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, string VecSize> { 2395 (!cast<Instruction>("SI_INDIRECT_SRC_"#VecSize) $src, $idx, imm:$offset) 2401 (!cast<Instruction>("SI_INDIRECT_DST_"#VecSize) $src, $idx, imm:$offset, $val)
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/freebsd/contrib/llvm-project/clang/lib/CodeGen/Targets/ |
H A D | Hexagon.cpp | 148 uint64_t VecSize = T.hasFeature("hvx-length64b") ? 64*8 : 128*8; in classifyReturnType() local 149 if (Size == VecSize || Size == 2*VecSize) in classifyReturnType()
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H A D | ARM.cpp | 731 unsigned VecSize = getContext().getTypeSize(VT); in isHomogeneousAggregateBaseType() local 732 if (VecSize == 64 || VecSize == 128) in isHomogeneousAggregateBaseType()
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H A D | AArch64.cpp | 493 unsigned VecSize = getContext().getTypeSize(VT); in isHomogeneousAggregateBaseType() local 494 if (VecSize == 64 || VecSize == 128) in isHomogeneousAggregateBaseType()
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H A D | X86.cpp | 67 unsigned VecSize = Context.getTypeSize(VT); in isX86VectorTypeForVectorCall() local 68 if (VecSize == 128 || VecSize == 256 || VecSize == 512) in isX86VectorTypeForVectorCall()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMBaseInfo.h | 437 VecSize = 3 << VecSizeShift, enumerator
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 2029 unsigned VecSize; in tryLoadParam() local 2034 VecSize = 1; in tryLoadParam() 2037 VecSize = 2; in tryLoadParam() 2040 VecSize = 4; in tryLoadParam() 2049 switch (VecSize) { in tryLoadParam() 2076 if (VecSize == 1) { in tryLoadParam() 2078 } else if (VecSize == 2) { in tryLoadParam()
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H A D | NVPTXReplaceImageHandles.cpp | 1761 unsigned VecSize = in processInstr() local 1765 MachineOperand &SurfHandle = MI.getOperand(VecSize); in processInstr()
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H A D | NVPTXAsmPrinter.cpp | 177 unsigned VecSize = in lowerImageHandleOperand() local 181 if (OpNo == VecSize && MO.isImm()) { in lowerImageHandleOperand()
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/freebsd/contrib/llvm-project/clang/lib/Sema/ |
H A D | SemaType.cpp | 2774 std::optional<llvm::APSInt> VecSize = in BuildVectorType() local 2776 if (!VecSize) { in BuildVectorType() 2788 if (!VecSize->isIntN(61)) { in BuildVectorType() 2794 uint64_t VectorSizeBits = VecSize->getZExtValue() * 8; in BuildVectorType() 8557 if (VecSize != S.getLangOpts().VScaleMin * 128) { in HandleArmSveVectorBitsTypeAttr() 8559 << VecSize << S.getLangOpts().VScaleMin * 128; in HandleArmSveVectorBitsTypeAttr() 8582 VecSize /= TypeSize; in HandleArmSveVectorBitsTypeAttr() 8657 NumElts = VecSize / S.Context.getCharWidth(); in HandleRISCVRVVVectorBitsTypeAttr() 8661 NumElts = VecSize / EltSize; in HandleRISCVRVVVectorBitsTypeAttr() 8665 if (ExpectedSize % 8 != 0 || VecSize != ExpectedSize) { in HandleRISCVRVVVectorBitsTypeAttr() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineVectorOps.cpp | 1185 int VecSize = in isShuffleEquivalentToSelect() local 1189 if (MaskSize != VecSize) in isShuffleEquivalentToSelect() 1196 if (Elt != -1 && Elt != i && Elt != i + VecSize) in isShuffleEquivalentToSelect()
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/freebsd/contrib/llvm-project/llvm/lib/IR/ |
H A D | Constants.cpp | 1277 unsigned VecSize = V.size(); in getTypeForElements() local 1278 SmallVector<Type*, 16> EltTypes(VecSize); in getTypeForElements() 1279 for (unsigned i = 0; i != VecSize; ++i) in getTypeForElements()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetTransformInfo.cpp | 1741 size_t VecSize = Vec.size(); in SimplifyValuePattern() local 1742 if (VecSize == 1) in SimplifyValuePattern() 1744 if (!isPowerOf2_64(VecSize)) in SimplifyValuePattern() 1746 size_t HalfVecSize = VecSize / 2; in SimplifyValuePattern()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMLowOverheadLoops.cpp | 109 return (Flags & ARMII::VecSize) >> ARMII::VecSizeShift; in getVecSize()
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H A D | ARMInstrFormats.td | 414 bits<2> VecSize = 0; 435 let TSFlags{25-24} = VecSize;
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 6858 const unsigned VecSize = 16; in CC_AIX() local 6859 const Align VecAlign(VecSize); in CC_AIX() 6871 const unsigned Offset = State.AllocateStack(VecSize, VecAlign); in CC_AIX() 6900 for (unsigned I = 0; I != VecSize; I += PtrSize) in CC_AIX() 6902 State.AllocateStack(VecSize, VecAlign); in CC_AIX() 6906 const unsigned Offset = State.AllocateStack(VecSize, VecAlign); in CC_AIX() 6913 const unsigned Offset = State.AllocateStack(VecSize, VecAlign); in CC_AIX() 6922 const unsigned Offset = State.AllocateStack(VecSize, VecAlign); in CC_AIX() 6940 const unsigned Offset = State.AllocateStack(VecSize, VecAlign); in CC_AIX() 6943 for (unsigned I = 0; I != VecSize; I += PtrSize) { in CC_AIX()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64InstructionSelector.cpp | 5390 unsigned VecSize = DstTy.getSizeInBits(); in selectInsertElt() local 5411 if (VecSize < 128) { in selectInsertElt() 5415 emitScalarToVector(VecSize, &AArch64::FPR128RegClass, SrcReg, MIB); in selectInsertElt() 5427 if (VecSize < 128) { in selectInsertElt()
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