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Searched refs:VirtReg (Results 1 – 25 of 46) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRegMatrix.cpp108 VRM->assignVirt2Phys(VirtReg.reg(), PhysReg); in assign()
113 Matrix[Unit].unify(VirtReg, Range); in assign()
122 Register PhysReg = VRM->getPhys(VirtReg.reg()); in unassign()
125 VRM->clearVirt(VirtReg.reg()); in unassign()
127 foreachUnit(TRI, VirtReg, PhysReg, in unassign()
152 RegMaskVirtReg = VirtReg.reg(); in checkRegMaskInterference()
166 if (VirtReg.empty()) in checkRegUnitInterference()
168 CoalescerPair CP(VirtReg.reg(), PhysReg, *TRI); in checkRegUnitInterference()
188 if (VirtReg.empty()) in checkInterference()
192 if (checkRegMaskInterference(VirtReg, PhysReg)) in checkInterference()
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H A DRegAllocFast.cpp211 explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {} in LiveReg()
405 bool mayLiveOut(Register VirtReg);
406 bool mayLiveIn(Register VirtReg);
548 VirtReg); in spill()
814 Register VirtReg = LR.VirtReg; in assignVirtToPhysReg() local
820 setPhysRegState(PhysReg, VirtReg); in assignVirtToPhysReg()
866 const Register VirtReg = LR.VirtReg; in allocVirtReg() local
955 Register VirtReg = MO.getReg(); in allocVirtRegUndef() local
1030 if (mayLiveOut(VirtReg)) { in defineVirtReg()
1107 if (mayLiveOut(VirtReg)) { in useVirtReg()
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H A DRegAllocBasic.cpp99 MCRegister selectOrSplit(const LiveInterval &VirtReg,
146 bool RABasic::LRE_CanEraseVirtReg(Register VirtReg) { in INITIALIZE_PASS_DEPENDENCY()
147 LiveInterval &LI = LIS->getInterval(VirtReg); in INITIALIZE_PASS_DEPENDENCY()
148 if (VRM->hasPhys(VirtReg)) { in INITIALIZE_PASS_DEPENDENCY()
161 void RABasic::LRE_WillShrinkVirtReg(Register VirtReg) { in LRE_WillShrinkVirtReg() argument
162 if (!VRM->hasPhys(VirtReg)) in LRE_WillShrinkVirtReg()
166 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_WillShrinkVirtReg()
270 switch (Matrix->checkInterference(VirtReg, PhysReg)) { in selectOrSplit()
288 if (!spillInterferences(VirtReg, PhysReg, SplitVRegs)) in selectOrSplit()
298 LLVM_DEBUG(dbgs() << "spilling: " << VirtReg << '\n'); in selectOrSplit()
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H A DRegAllocBase.cpp88 while (const LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
92 if (MRI->reg_nodbg_empty(VirtReg->reg())) { in allocatePhysRegs()
93 LLVM_DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n'); in allocatePhysRegs()
94 aboutToRemoveInterval(*VirtReg); in allocatePhysRegs()
95 LIS->removeInterval(VirtReg->reg()); in allocatePhysRegs()
107 << ':' << *VirtReg << " w=" << VirtReg->weight() << '\n'); in allocatePhysRegs()
112 MCRegister AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs); in allocatePhysRegs()
119 I = MRI->reg_instr_begin(VirtReg->reg()), in allocatePhysRegs()
127 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg->reg()); in allocatePhysRegs()
142 VRM->assignVirt2Phys(VirtReg->reg(), AllocOrder.front()); in allocatePhysRegs()
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H A DRegAllocGreedy.cpp238 if (VRM->hasPhys(VirtReg)) { in LRE_CanEraseVirtReg()
252 if (!VRM->hasPhys(VirtReg)) in LRE_WillShrinkVirtReg()
1248 Register Reg = VirtReg.reg(); in trySplitAroundHintReg()
1279 SA->analyze(&VirtReg); in trySplitAroundHintReg()
1811 SA->analyze(&VirtReg); in trySplit()
1821 SA->analyze(&VirtReg); in trySplit()
1970 assert((ExtraInfo->getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) && in tryLastChanceRecoloring()
2057 Matrix->unassign(VirtReg); in tryLastChanceRecoloring()
2179 if (ExtraInfo->getStage(VirtReg) == RS_Spill && VirtReg.isSpillable()) { in tryAssignCSRFirstTime()
2182 SA->analyze(&VirtReg); in tryAssignCSRFirstTime()
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H A DRegAllocEvictionAdvisor.cpp168 const LiveInterval &VirtReg, MCRegister PhysReg, in canEvictHintInterference() argument
172 return canEvictInterferenceBasedOnCost(VirtReg, PhysReg, true, MaxCost, in canEvictHintInterference()
186 const LiveInterval &VirtReg, MCRegister PhysReg, bool IsHint, in canEvictInterferenceBasedOnCost() argument
192 bool IsLocal = VirtReg.empty() || LIS->intervalIsInOneMBB(VirtReg); in canEvictInterferenceBasedOnCost()
205 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit); in canEvictInterferenceBasedOnCost()
232 !VirtReg.isSpillable() && in canEvictInterferenceBasedOnCost()
260 if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint)) in canEvictInterferenceBasedOnCost()
276 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate() argument
282 auto MaybeOrderLimit = getOrderLimit(VirtReg, Order, CostPerUseLimit); in tryFindEvictionCandidate()
291 BestCost.MaxWeight = VirtReg.weight(); in tryFindEvictionCandidate()
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H A DLiveIntervalUnion.cpp28 void LiveIntervalUnion::unify(const LiveInterval &VirtReg, in unify() argument
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
50 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg); in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
56 void LiveIntervalUnion::extract(const LiveInterval &VirtReg, in extract() argument
68 assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval"); in extract()
116 const LiveInterval *VirtReg) const { in isSeenInterference()
117 return is_contained(InterferingVRegs, VirtReg); in isSeenInterference()
H A DMLRegAllocEvictAdvisor.cpp306 tryFindEvictionCandidatePosition(const LiveInterval &VirtReg,
323 const LiveInterval &VirtReg, const AllocationOrder &Order,
335 const LiveInterval &VirtReg, MCRegister PhysReg, in canEvictHintInterference() argument
439 const LiveInterval &VirtReg, const AllocationOrder &Order,
597 const LiveInterval &VirtReg, MCRegister PhysReg, bool IsHint, in loadInterferenceFeatures() argument
607 const bool IsLocal = LIS->intervalIsInOneMBB(VirtReg); in loadInterferenceFeatures()
616 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit); in loadInterferenceFeatures()
639 !VirtReg.isSpillable() && in loadInterferenceFeatures()
664 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate() argument
1085 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidatePosition() argument
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H A DRegAllocGreedy.h86 LiveRangeStage getStage(const LiveInterval &VirtReg) const { in getStage() argument
87 return getStage(VirtReg.reg()); in getStage()
95 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument
96 setStage(VirtReg.reg(), Stage); in setStage()
338 const LiveInterval &VirtReg,
356 unsigned calculateRegionSplitCost(const LiveInterval &VirtReg,
361 unsigned doRegionSplit(const LiveInterval &VirtReg, unsigned BestCand,
364 bool trySplitAroundHintReg(MCPhysReg Hint, const LiveInterval &VirtReg,
369 MCRegister tryAssignCSRFirstTime(const LiveInterval &VirtReg,
H A DAllocationOrder.cpp29 AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM, in create() argument
34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create()
37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix); in create()
H A DVirtRegMap.cpp109 bool VirtRegMap::hasPreferredPhys(Register VirtReg) const { in hasPreferredPhys()
110 Register Hint = MRI->getSimpleHint(VirtReg); in hasPreferredPhys()
115 return Register(getPhys(VirtReg)) == Hint; in hasPreferredPhys()
118 bool VirtRegMap::hasKnownPreference(Register VirtReg) const { in hasKnownPreference()
119 std::pair<unsigned, Register> Hint = MRI->getRegAllocationHint(VirtReg); in hasKnownPreference()
342 Register VirtReg = Register::index2VirtReg(Idx); in addMBBLiveIns() local
343 if (MRI->reg_nodbg_empty(VirtReg)) in addMBBLiveIns()
345 LiveInterval &LI = LIS->getInterval(VirtReg); in addMBBLiveIns()
350 Register PhysReg = VRM->getPhys(VirtReg); in addMBBLiveIns()
552 Register VirtReg = MO.getReg(); in rewrite() local
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H A DRegAllocEvictionAdvisor.h108 const LiveInterval &VirtReg, const AllocationOrder &Order,
114 canEvictHintInterference(const LiveInterval &VirtReg, MCRegister PhysReg,
124 bool canReassign(const LiveInterval &VirtReg, MCRegister FromReg) const;
128 std::optional<unsigned> getOrderLimit(const LiveInterval &VirtReg,
H A DRegisterCoalescer.h64 CoalescerPair(Register VirtReg, MCRegister PhysReg, in CoalescerPair() argument
66 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg) {} in CoalescerPair()
H A DLiveDebugVariables.cpp591 UserValue *lookupVirtReg(Register VirtReg);
659 void mapVirtReg(Register VirtReg, UserValue *EC);
788 void LDVImpl::mapVirtReg(Register VirtReg, UserValue *EC) { in mapVirtReg() argument
789 assert(VirtReg.isVirtual() && "Only map VirtRegs"); in mapVirtReg()
790 UserValue *&Leader = virtRegToEqClass[VirtReg]; in mapVirtReg()
794 UserValue *LDVImpl::lookupVirtReg(Register VirtReg) { in lookupVirtReg() argument
795 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg)) in lookupVirtReg()
1531 Register VirtReg = Loc.getReg(); in rewriteLocations() local
1532 if (VRM.isAssignedReg(VirtReg) && in rewriteLocations()
1533 Register::isPhysicalRegister(VRM.getPhys(VirtReg))) { in rewriteLocations()
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H A DTargetRegisterInfo.cpp71 const MachineFunction &MF, const LiveInterval &VirtReg) const { in shouldRegionSplitForVirtReg()
74 MachineInstr *MI = MRI.getUniqueVRegDef(VirtReg.reg()); in shouldRegionSplitForVirtReg()
76 VirtReg.size() > HugeSizeForSplit) in shouldRegionSplitForVirtReg()
424 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints() argument
429 MRI.getRegAllocationHints(VirtReg); in getRegAllocationHints()
H A DPHIElimination.cpp164 Register VirtReg = Register::index2VirtReg(Index); in runOnMachineFunction() local
165 MachineInstr *DefMI = MRI->getVRegDef(VirtReg); in runOnMachineFunction()
168 LiveVariables::VarInfo &VI = LV->getVarInfo(VirtReg); in runOnMachineFunction()
250 static bool isImplicitlyDefined(unsigned VirtReg, in isImplicitlyDefined() argument
252 for (MachineInstr &DI : MRI.def_instructions(VirtReg)) in isImplicitlyDefined()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRegMatrix.h107 InterferenceKind checkInterference(const LiveInterval &VirtReg,
120 void assign(const LiveInterval &VirtReg, MCRegister PhysReg);
125 void unassign(const LiveInterval &VirtReg);
140 bool checkRegMaskInterference(const LiveInterval &VirtReg,
146 bool checkRegUnitInterference(const LiveInterval &VirtReg,
H A DVirtRegMap.h145 bool hasPreferredPhys(Register VirtReg) const;
150 bool hasKnownPreference(Register VirtReg) const;
169 Register getOriginal(Register VirtReg) const { in getOriginal() argument
170 Register Orig = getPreSplitReg(VirtReg); in getOriginal()
171 return Orig ? Orig : VirtReg; in getOriginal()
H A DLiveIntervalUnion.h91 void unify(const LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(const LiveInterval &VirtReg, const LiveRange &Range);
128 bool isSeenInterference(const LiveInterval *VirtReg) const;
H A DScheduleDAGInstrs.h54 unsigned VirtReg; member
59 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {} in VReg2SUnit()
62 return Register::virtReg2Index(VirtReg); in getSparseSetIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastPreTileConfig.cpp68 int getStackSpaceFor(Register VirtReg);
70 bool mayLiveOut(Register VirtReg, MachineInstr *CfgMI);
118 int X86FastPreTileConfig::getStackSpaceFor(Register VirtReg) { in getStackSpaceFor() argument
120 int SS = StackSlotForVirtReg[VirtReg]; in getStackSpaceFor()
126 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in getStackSpaceFor()
132 StackSlotForVirtReg[VirtReg] = FrameIdx; in getStackSpaceFor()
145 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); in mayLiveOut()
202 Register VirtReg, bool Kill) { in spill() argument
204 int FI = getStackSpaceFor(VirtReg); in spill()
207 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in spill()
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H A DX86TileConfig.cpp121 Register VirtReg = Register::index2VirtReg(I); in INITIALIZE_PASS_DEPENDENCY() local
122 if (MRI.reg_nodbg_empty(VirtReg)) in INITIALIZE_PASS_DEPENDENCY()
124 if (MRI.getRegClass(VirtReg)->getID() != X86::TILERegClassID) in INITIALIZE_PASS_DEPENDENCY()
126 if (VRM.getPhys(VirtReg) == VirtRegMap::NO_PHYS_REG) in INITIALIZE_PASS_DEPENDENCY()
128 unsigned Index = VRM.getPhys(VirtReg) - X86::TMM0; in INITIALIZE_PASS_DEPENDENCY()
130 Phys2Virt[Index] = VirtReg; in INITIALIZE_PASS_DEPENDENCY()
H A DX86RegisterInfo.cpp1030 static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM, in getTileShape() argument
1032 if (VRM->hasShape(VirtReg)) in getTileShape()
1033 return VRM->getShape(VirtReg); in getTileShape()
1035 const MachineOperand &Def = *MRI->def_begin(VirtReg); in getTileShape()
1045 VRM->assignVirt2Shape(VirtReg, Shape); in getTileShape()
1063 VRM->assignVirt2Shape(VirtReg, Shape); in getTileShape()
1068 bool X86RegisterInfo::getRegAllocationHints(Register VirtReg, in getRegAllocationHints() argument
1075 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in getRegAllocationHints()
1077 VirtReg, Order, Hints, MF, VRM, Matrix); in getRegAllocationHints()
1083 ShapeT VirtShape = getTileShape(VirtReg, const_cast<VirtRegMap *>(VRM), MRI); in getRegAllocationHints()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp75 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints() argument
83 VirtReg, Order, Hints, MF, VRM, Matrix); in getRegAllocationHints()
88 for (auto &Use : MRI->reg_nodbg_instructions(VirtReg)) in getRegAllocationHints()
93 if (VirtReg == Use.getOperand(0).getReg()) { in getRegAllocationHints()
98 } else if (VirtReg == Use.getOperand(1).getReg()) { in getRegAllocationHints()
101 } else if (VirtReg == Use.getOperand(2).getReg() && in getRegAllocationHints()
117 MRI->getRegClass(VirtReg)); in getRegAllocationHints()
131 if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) { in getRegAllocationHints()
134 Worklist.push_back(VirtReg); in getRegAllocationHints()
173 for (MachineInstr &DefMI : MRI->def_instructions(VirtReg)) in getRegAllocationHints()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPreAllocateWWMRegs.cpp125 const Register VirtReg = MO.getReg(); in rewriteRegs() local
126 if (VirtReg.isPhysical()) in rewriteRegs()
129 if (!VRM->hasPhys(VirtReg)) in rewriteRegs()
132 Register PhysReg = VRM->getPhys(VirtReg); in rewriteRegs()

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