| /freebsd/sys/dev/hdmi/ |
| H A D | dwc_hdmi.c | 95 WR1(sc, HDMI_IH_I2CMPHY_STAT0, in dwc_hdmi_phy_i2c_write()
108 WR1(sc, HDMI_FC_MASK2, in dwc_hdmi_disable_overflow_interrupts()
189 WR1(sc, HDMI_PHY_CONF0, reg); in dwc_hdmi_phy_enable_power()
200 WR1(sc, HDMI_PHY_CONF0, reg); in dwc_hdmi_phy_enable_tmds()
211 WR1(sc, HDMI_PHY_CONF0, reg); in dwc_hdmi_phy_gen2_pddq()
222 WR1(sc, HDMI_PHY_CONF0, reg); in dwc_hdmi_phy_gen2_txpwron()
233 WR1(sc, HDMI_PHY_CONF0, reg); in dwc_hdmi_phy_sel_data_en_pol()
256 WR1(sc, HDMI_PHY_TST0, val); in dwc_hdmi_phy_test_clear()
469 WR1(sc, HDMI_AUD_CTS3, val); in dwc_hdmi_configure_audio()
525 WR1(sc, HDMI_VP_CONF, val); in dwc_hdmi_video_packetize()
[all …]
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| H A D | dwc_hdmi.h | 52 WR1(struct dwc_hdmi_softc *sc, bus_size_t off, uint8_t val) in WR1() function
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| /freebsd/sys/arm64/nvidia/tegra210/ |
| H A D | max77620_gpio.c | 259 rv = WR1(sc, pin->reg, reg); in max77620_pinmux_config_node()
357 rv = WR1(sc, MAX77620_REG_PUE_GPIO, sc->gpio_reg_pue); in max77620_pinmux_configure()
366 rv = WR1(sc, MAX77620_REG_PDE_GPIO, sc->gpio_reg_pde); in max77620_pinmux_configure()
375 rv = WR1(sc, MAX77620_REG_AME_GPIO, sc->gpio_reg_ame); in max77620_pinmux_configure()
560 rv = WR1(sc, pin->reg, reg); in max77620_gpio_pin_setflags()
566 rv = WR1(sc, MAX77620_REG_PUE_GPIO, sc->gpio_reg_pue); in max77620_gpio_pin_setflags()
576 rv = WR1(sc, MAX77620_REG_PDE_GPIO, sc->gpio_reg_pde); in max77620_gpio_pin_setflags()
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| H A D | max77620.h | 225 #define WR1(sc, reg, val) max77620_write(sc, reg, val) macro
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| /freebsd/sys/arm/nvidia/ |
| H A D | as3722.c | 233 rv = WR1(sc, AS3722_INTERRUPT_MASK1, 0); in as3722_init()
236 rv = WR1(sc, AS3722_INTERRUPT_MASK2, 0); in as3722_init()
239 rv = WR1(sc, AS3722_INTERRUPT_MASK3, 0); in as3722_init()
242 rv = WR1(sc, AS3722_INTERRUPT_MASK4, 0); in as3722_init()
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| H A D | as3722_gpio.c | 197 rv = WR1(sc, AS3722_GPIO0_CONTROL + pin, ctrl); in as3722_pinmux_config_node()
444 rv = WR1(sc, AS3722_GPIO0_CONTROL + pin, ctrl); in as3722_gpio_pin_setflags()
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| H A D | as3722.h | 284 #define WR1(sc, reg, val) as3722_write(sc, reg, val) macro
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| /freebsd/sys/dev/iicbus/pmic/ |
| H A D | act8846.h | 48 #define WR1(sc, reg, val) act8846_write(sc, reg, val) macro
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| /freebsd/sys/dev/sdhci/ |
| H A D | sdhci.c | 521 WR1(slot, SDHCI_POWER_CONTROL, pwr); in sdhci_set_power()
539 WR1(slot, SDHCI_POWER_CONTROL, pwr); in sdhci_set_power()
547 WR1(slot, SDHCI_POWER_CONTROL, pwr); in sdhci_set_power()
556 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); in sdhci_set_power()
558 WR1(slot, SDHCI_POWER_CONTROL, pwr); in sdhci_set_power()
1267 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
1389 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
1950 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
2183 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
2195 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
[all …]
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| /freebsd/sys/dev/iicbus/controller/cadence/ |
| H A D | cdnc_i2c.c | 114 #define WR1(sc, off, val) (bus_write_1((sc)->mem_res, (off), (val))) macro
246 WR1(sc, CDNC_I2C_TIME_OUT, CDNC_I2C_TIME_OUT_MAX); in cdnc_i2c_init_hw()
353 WR1(sc, CDNC_I2C_TRANS_SIZE, nbytes); in cdnc_i2c_xfer_rd()
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| /freebsd/sys/arm/broadcom/bcm2835/ |
| H A D | bcm2835_sdhost.c | 283 WR1(struct bcm_sdhost_softc *sc, bus_size_t off, uint8_t val) in WR1() function
1056 WR1(sc, HC_POWER, val2); in bcm_sdhost_write_1()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 627 Hexagon::W0, Hexagon::WR0, Hexagon::W1, Hexagon::WR1, Hexagon::W2, in DecodeHvxWRRegisterClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.td | 253 def WR1 : Rd< 3, "v2:3", [V2, V3, VFR1]>, DwarfRegNum<[162]>;
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