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Searched refs:cfg1 (Results 1 – 25 of 30) sorted by relevance

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/freebsd/sys/dev/ata/chipsets/
H A Data-highpoint.c93 if (idx->cfg1 == HPT_374) { in ata_highpoint_probe()
127 if (ctlr->chip->cfg1 < HPT_372) in ata_highpoint_chipinit()
150 if (ctlr->chip->cfg1 == HPT_366) in ata_highpoint_ch_attach()
190 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); in ata_highpoint_setmode()
202 if (ctlr->chip->cfg1 == HPT_374 && pci_get_function(parent) == 1) { in ata_highpoint_check_80pin()
H A Data-nvidia.c178 if ((ctlr->chip->cfg1 & NVAHCI) && in ata_nvidia_probe()
195 if (ctlr->chip->cfg1 & NVAHCI) { in ata_nvidia_chipinit()
206 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; in ata_nvidia_chipinit()
216 if (ctlr->chip->cfg1 & NVQ) { in ata_nvidia_chipinit()
285 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; in ata_nvidia_status()
286 int shift = ch->unit << (ctlr->chip->cfg1 & NVQ ? 4 : 2); in ata_nvidia_status()
290 if (ctlr->chip->cfg1 & NVQ) in ata_nvidia_status()
300 if (ctlr->chip->cfg1 & NVQ) in ata_nvidia_status()
H A Data-sis.c122 id[0].cfg1 = SIS_133NEW; in ata_sis_probe()
136 id[0].cfg1 = SIS_133OLD; in ata_sis_probe()
139 id[0].cfg1 = SIS_100NEW; in ata_sis_probe()
166 switch (ctlr->chip->cfg1) { in ata_sis_chipinit()
246 if (ctlr->chip->cfg1 == SIS_133NEW) { in ata_sis_setmode()
260 switch (ctlr->chip->cfg1) { in ata_sis_setmode()
H A Data-amd.c96 if (ctlr->chip->cfg1 & AMD_BUG) in ata_amd_chipinit()
121 if (ctlr->chip->cfg1 & AMD_CABLE) { in ata_amd_setmode()
151 if (ctlr->chip->cfg1 & AMD_CABLE) in ata_amd_ch_attach()
H A Data-serverworks.c130 if (ctlr->chip->cfg1 == SWKS_MIO) { in ata_serverworks_chipinit()
145 else if (ctlr->chip->cfg1 == SWKS_33) { in ata_serverworks_chipinit()
164 ((ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02), 1); in ata_serverworks_chipinit()
357 if (ctlr->chip->cfg1 != SWKS_33) { in ata_serverworks_setmode()
H A Data-ati.c103 switch (ctlr->chip->cfg1) { in ata_ati_probe()
134 if (ctlr->chip->cfg1 == ATI_AHCI) { in ata_ati_chipinit()
H A Data-intel.c267 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { in ata_intel_chipinit()
289 (ctlr->chip->cfg1 & INTEL_ICH5)) in ata_intel_chipinit()
336 if (ctlr->chip->cfg1 & INTEL_ICH5) { in ata_intel_ch_attach()
352 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { in ata_intel_ch_attach()
374 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { in ata_intel_ch_attach()
378 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { in ata_intel_ch_attach()
431 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) in ata_intel_reset()
H A Data-via.c248 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); in ata_via_ch_attach()
250 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); in ata_via_ch_attach()
252 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); in ata_via_ch_attach()
362 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); in ata_via_old_setmode()
H A Data-jmicron.c112 if (ctlr->chip->cfg1) { in ata_jmicron_chipinit()
H A Data-marvell.c127 if (ctlr->chip->cfg1) { in ata_marvell_chipinit()
H A Data-acard.c98 if (ctlr->chip->cfg1 == ATP_OLD) { in ata_acard_chipinit()
H A Data-promise.c221 switch (ctlr->chip->cfg1) { in ata_promise_chipinit()
364 if (ctlr->chip->cfg1 == PR_NEW) { in ata_promise_ch_attach()
469 switch (ctlr->chip->cfg1) { in ata_promise_setmode()
500 if (ctlr->chip->cfg1 < PR_TX) in ata_promise_setmode()
502 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); in ata_promise_setmode()
H A Data-acerlabs.c113 ctlr->channels = ctlr->chip->cfg1; in ata_ali_chipinit()
H A Data-siliconimage.c110 switch (ctlr->chip->cfg1) { in ata_sii_chipinit()
/freebsd/sys/arm64/freescale/imx/clk/
H A Dimx_clk_frac_pll.c116 uint32_t cfg0, cfg1; in imx_clk_frac_pll_recalc() local
123 READ4(clk, sc->offset + CFG1, &cfg1); in imx_clk_frac_pll_recalc()
128 divff = (cfg1 & CFG1_FRAC_DIV_MASK) >> CFG1_FRAC_DIV_SHIFT; in imx_clk_frac_pll_recalc()
129 divfi = (cfg1 & CFG1_INT_DIV_MASK) >> CFG1_INT_DIV_SHIFT; in imx_clk_frac_pll_recalc()
/freebsd/sys/dev/bhnd/nvram/
H A Dbhnd_nvram_data_bcmreg.h58 #define BCM_NVRAM_CFG1_SDRAM_CFG_FIELD cfg1
64 #define BCM_NVRAM_CFG1_SDRAM_REFRESH_FIELD cfg1
H A Dbhnd_nvram_data_bcmvar.h66 uint32_t cfg1; /**< sdram_config:16, sdram_refresh:16 */ member
H A Dbhnd_nvram_data_bcm.c431 .cfg1 = 0, in bhnd_nvram_bcm_serialize()
440 hdr.cfg1 = BCM_NVRAM_SET_BITS(hdr.cfg1, BCM_NVRAM_CFG1_SDRAM_CFG, in bhnd_nvram_bcm_serialize()
442 hdr.cfg1 = BCM_NVRAM_SET_BITS(hdr.cfg1, BCM_NVRAM_CFG1_SDRAM_REFRESH, in bhnd_nvram_bcm_serialize()
/freebsd/sys/contrib/dev/mediatek/mt76/mt76x2/
H A Dphy.c187 u32 cfg0, cfg1; in mt76x2_configure_tx_delay() local
191 cfg1 = 0x00011414; in mt76x2_configure_tx_delay()
194 cfg1 = 0x00021414; in mt76x2_configure_tx_delay()
197 mt76_wr(dev, MT_TX_SW_CFG1, cfg1); in mt76x2_configure_tx_delay()
/freebsd/sys/dev/qlnx/qlnxe/
H A Dspad_layout.h205 #define NVM_CFG1(x) g_spad.nvm_cfg.cfg1.x
/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dti,j72xx-thermal.yaml33 - description: VTM cfg1 register space
/freebsd/sys/dev/et/
H A Dif_et.c505 uint32_t cfg1, cfg2, ctrl; in et_miibus_statchg() local
538 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
539 cfg1 &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | in et_miibus_statchg()
570 cfg1 |= ET_MAC_CFG1_TXFLOW; in et_miibus_statchg()
573 cfg1 |= ET_MAC_CFG1_RXFLOW; in et_miibus_statchg()
579 cfg1 |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; in et_miibus_statchg()
580 CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1); in et_miibus_statchg()
585 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
586 if ((cfg1 & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == in et_miibus_statchg()
/freebsd/sys/dev/ata/
H A Data-pci.h33 int cfg1; member
/freebsd/sys/contrib/dev/athk/ath11k/
H A Ddp.h1573 u32 cfg1; member
H A Ddebugfs_htt_stats.c4672 cfg_params->cfg1 = HTT_STAT_DEFAULT_PEER_REQ_TYPE; in ath11k_prep_htt_stats_cfg_params()
4695 cfg_params->cfg1 |= FIELD_PREP(GENMASK(7, 0), mac_addr[0]); in ath11k_prep_htt_stats_cfg_params()
4696 cfg_params->cfg1 |= FIELD_PREP(GENMASK(15, 8), mac_addr[1]); in ath11k_prep_htt_stats_cfg_params()
4697 cfg_params->cfg1 |= FIELD_PREP(GENMASK(23, 16), mac_addr[2]); in ath11k_prep_htt_stats_cfg_params()
4698 cfg_params->cfg1 |= FIELD_PREP(GENMASK(31, 24), mac_addr[3]); in ath11k_prep_htt_stats_cfg_params()
4868 cfg_params.cfg1 = 1 << (cfg_params.cfg0 + type); in ath11k_write_htt_stats_reset()

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