Searched refs:hw_ecap (Results 1 – 7 of 7) sorted by relevance
/freebsd/sys/x86/iommu/ |
H A D | intel_dmar.h | 138 uint64_t hw_ecap; member 216 #define DMAR_IS_COHERENT(dmar) (((dmar)->hw_ecap & DMAR_ECAP_C) != 0) 217 #define DMAR_HAS_QI(dmar) (((dmar)->hw_ecap & DMAR_ECAP_QI) != 0) 219 (x2apic_mode && ((dmar)->hw_ecap & DMAR_ECAP_EIM) != 0)
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H A D | intel_ctx.c | 185 (unit->hw_ecap & DMAR_ECAP_PT) != 0) { in ctx_id_entry_init() 219 if ((dmar->hw_ecap & DMAR_ECAP_DI) != 0 || force) in dmar_flush_for_ctx_entry() 224 if (error == 0 && ((dmar->hw_ecap & DMAR_ECAP_DI) != 0 || force)) in dmar_flush_for_ctx_entry() 417 if ((dmar->hw_ecap & DMAR_ECAP_PT) == 0) { in dmar_domain_alloc() 807 if ((dmar->hw_ecap & DMAR_ECAP_DI) != 0) { in dmar_free_ctx_locked()
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H A D | intel_drv.c | 394 ecaphi = unit->hw_ecap >> 32; in dmar_print_caps() 395 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap, in dmar_print_caps() 399 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap), in dmar_print_caps() 400 DMAR_ECAP_IRO(unit->hw_ecap)); in dmar_print_caps() 429 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG); in dmar_attach() 507 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) { in dmar_attach()
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H A D | intel_idpgtbl.c | 539 (unit->hw_ecap & DMAR_ECAP_SC) != 0, in domain_map_buf() 543 (unit->hw_ecap & DMAR_ECAP_DI) != 0, in domain_map_buf() 728 KASSERT((domain->dmar->hw_ecap & DMAR_ECAP_PT) != 0 && in domain_free_pgtbl() 778 iro = DMAR_ECAP_IRO(unit->hw_ecap) * 16; in domain_flush_iotlb_sync()
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H A D | intel_quirks.c | 160 unit->hw_ecap &= ~(DMAR_ECAP_IR | DMAR_ECAP_EIM); in nb_no_ir()
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H A D | intel_intrmap.c | 329 if ((unit->hw_ecap & DMAR_ECAP_IR) == 0) in dmar_init_irt()
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H A D | intel_utils.c | 359 reg = 16 * DMAR_ECAP_IRO(unit->hw_ecap); in dmar_inv_iotlb_glob()
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