1 /*-
2 * Copyright (c) 2015 The FreeBSD Foundation
3 *
4 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
5 * under sponsorship from the FreeBSD Foundation.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/kernel.h>
33 #include <sys/lock.h>
34 #include <sys/malloc.h>
35 #include <sys/memdesc.h>
36 #include <sys/mutex.h>
37 #include <sys/rman.h>
38 #include <sys/rwlock.h>
39 #include <sys/sysctl.h>
40 #include <sys/taskqueue.h>
41 #include <sys/tree.h>
42 #include <sys/vmem.h>
43 #include <vm/vm.h>
44 #include <vm/vm_extern.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_object.h>
47 #include <vm/vm_page.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/pci/pcivar.h>
50 #include <machine/bus.h>
51 #include <machine/intr_machdep.h>
52 #include <x86/include/apicreg.h>
53 #include <x86/include/apicvar.h>
54 #include <x86/include/busdma_impl.h>
55 #include <dev/iommu/busdma_iommu.h>
56 #include <x86/iommu/intel_reg.h>
57 #include <x86/iommu/intel_dmar.h>
58 #include <x86/iommu/iommu_intrmap.h>
59
60 static struct dmar_unit *dmar_ir_find(device_t src, uint16_t *rid,
61 int *is_dmar);
62 static void dmar_ir_program_irte(struct dmar_unit *unit, u_int idx,
63 uint64_t low, uint16_t rid);
64 static int dmar_ir_free_irte(struct dmar_unit *unit, u_int cookie);
65
66 int
iommu_alloc_msi_intr(device_t src,u_int * cookies,u_int count)67 iommu_alloc_msi_intr(device_t src, u_int *cookies, u_int count)
68 {
69 struct dmar_unit *unit;
70 vmem_addr_t vmem_res;
71 u_int idx, i;
72 int error;
73
74 unit = dmar_ir_find(src, NULL, NULL);
75 if (unit == NULL || !unit->ir_enabled) {
76 for (i = 0; i < count; i++)
77 cookies[i] = -1;
78 return (EOPNOTSUPP);
79 }
80
81 error = vmem_alloc(unit->irtids, count, M_FIRSTFIT | M_NOWAIT,
82 &vmem_res);
83 if (error != 0) {
84 KASSERT(error != EOPNOTSUPP,
85 ("impossible EOPNOTSUPP from vmem"));
86 return (error);
87 }
88 idx = vmem_res;
89 for (i = 0; i < count; i++)
90 cookies[i] = idx + i;
91 return (0);
92 }
93
94 int
iommu_map_msi_intr(device_t src,u_int cpu,u_int vector,u_int cookie,uint64_t * addr,uint32_t * data)95 iommu_map_msi_intr(device_t src, u_int cpu, u_int vector, u_int cookie,
96 uint64_t *addr, uint32_t *data)
97 {
98 struct dmar_unit *unit;
99 uint64_t low;
100 uint16_t rid;
101 int is_dmar;
102
103 unit = dmar_ir_find(src, &rid, &is_dmar);
104 if (is_dmar) {
105 KASSERT(unit == NULL, ("DMAR cannot translate itself"));
106
107 /*
108 * See VT-d specification, 5.1.6 Remapping Hardware -
109 * Interrupt Programming.
110 */
111 *data = vector;
112 *addr = MSI_INTEL_ADDR_BASE | ((cpu & 0xff) << 12);
113 if (x2apic_mode)
114 *addr |= ((uint64_t)cpu & 0xffffff00) << 32;
115 else
116 KASSERT(cpu <= 0xff, ("cpu id too big %d", cpu));
117 return (0);
118 }
119 if (unit == NULL || !unit->ir_enabled || cookie == -1)
120 return (EOPNOTSUPP);
121
122 low = (DMAR_X2APIC(unit) ? DMAR_IRTE1_DST_x2APIC(cpu) :
123 DMAR_IRTE1_DST_xAPIC(cpu)) | DMAR_IRTE1_V(vector) |
124 DMAR_IRTE1_DLM_FM | DMAR_IRTE1_TM_EDGE | DMAR_IRTE1_RH_DIRECT |
125 DMAR_IRTE1_DM_PHYSICAL | DMAR_IRTE1_P;
126 dmar_ir_program_irte(unit, cookie, low, rid);
127
128 if (addr != NULL) {
129 /*
130 * See VT-d specification, 5.1.5.2 MSI and MSI-X
131 * Register Programming.
132 */
133 *addr = MSI_INTEL_ADDR_BASE | ((cookie & 0x7fff) << 5) |
134 ((cookie & 0x8000) << 2) | 0x18;
135 *data = 0;
136 }
137 return (0);
138 }
139
140 int
iommu_unmap_msi_intr(device_t src,u_int cookie)141 iommu_unmap_msi_intr(device_t src, u_int cookie)
142 {
143 struct dmar_unit *unit;
144
145 if (cookie == -1)
146 return (0);
147 unit = dmar_ir_find(src, NULL, NULL);
148 return (dmar_ir_free_irte(unit, cookie));
149 }
150
151 int
iommu_map_ioapic_intr(u_int ioapic_id,u_int cpu,u_int vector,bool edge,bool activehi,int irq,u_int * cookie,uint32_t * hi,uint32_t * lo)152 iommu_map_ioapic_intr(u_int ioapic_id, u_int cpu, u_int vector, bool edge,
153 bool activehi, int irq, u_int *cookie, uint32_t *hi, uint32_t *lo)
154 {
155 struct dmar_unit *unit;
156 vmem_addr_t vmem_res;
157 uint64_t low, iorte;
158 u_int idx;
159 int error;
160 uint16_t rid;
161
162 unit = dmar_find_ioapic(ioapic_id, &rid);
163 if (unit == NULL || !unit->ir_enabled) {
164 *cookie = -1;
165 return (EOPNOTSUPP);
166 }
167
168 error = vmem_alloc(unit->irtids, 1, M_FIRSTFIT | M_NOWAIT, &vmem_res);
169 if (error != 0) {
170 KASSERT(error != EOPNOTSUPP,
171 ("impossible EOPNOTSUPP from vmem"));
172 return (error);
173 }
174 idx = vmem_res;
175 low = 0;
176 switch (irq) {
177 case IRQ_EXTINT:
178 low |= DMAR_IRTE1_DLM_ExtINT;
179 break;
180 case IRQ_NMI:
181 low |= DMAR_IRTE1_DLM_NMI;
182 break;
183 case IRQ_SMI:
184 low |= DMAR_IRTE1_DLM_SMI;
185 break;
186 default:
187 KASSERT(vector != 0, ("No vector for IRQ %u", irq));
188 low |= DMAR_IRTE1_DLM_FM | DMAR_IRTE1_V(vector);
189 break;
190 }
191 low |= (DMAR_X2APIC(unit) ? DMAR_IRTE1_DST_x2APIC(cpu) :
192 DMAR_IRTE1_DST_xAPIC(cpu)) |
193 (edge ? DMAR_IRTE1_TM_EDGE : DMAR_IRTE1_TM_LEVEL) |
194 DMAR_IRTE1_RH_DIRECT | DMAR_IRTE1_DM_PHYSICAL | DMAR_IRTE1_P;
195 dmar_ir_program_irte(unit, idx, low, rid);
196
197 if (hi != NULL) {
198 /*
199 * See VT-d specification, 5.1.5.1 I/OxAPIC
200 * Programming.
201 */
202 iorte = (1ULL << 48) | ((uint64_t)(idx & 0x7fff) << 49) |
203 ((idx & 0x8000) != 0 ? (1 << 11) : 0) |
204 (edge ? IOART_TRGREDG : IOART_TRGRLVL) |
205 (activehi ? IOART_INTAHI : IOART_INTALO) |
206 IOART_DELFIXED | vector;
207 *hi = iorte >> 32;
208 *lo = iorte;
209 }
210 *cookie = idx;
211 return (0);
212 }
213
214 int
iommu_unmap_ioapic_intr(u_int ioapic_id,u_int * cookie)215 iommu_unmap_ioapic_intr(u_int ioapic_id, u_int *cookie)
216 {
217 struct dmar_unit *unit;
218 u_int idx;
219
220 idx = *cookie;
221 if (idx == -1)
222 return (0);
223 *cookie = -1;
224 unit = dmar_find_ioapic(ioapic_id, NULL);
225 KASSERT(unit != NULL && unit->ir_enabled,
226 ("unmap: cookie %d unit %p", idx, unit));
227 return (dmar_ir_free_irte(unit, idx));
228 }
229
230 static struct dmar_unit *
dmar_ir_find(device_t src,uint16_t * rid,int * is_dmar)231 dmar_ir_find(device_t src, uint16_t *rid, int *is_dmar)
232 {
233 devclass_t src_class;
234 struct dmar_unit *unit;
235
236 /*
237 * We need to determine if the interrupt source generates FSB
238 * interrupts. If yes, it is either DMAR, in which case
239 * interrupts are not remapped. Or it is HPET, and interrupts
240 * are remapped. For HPET, source id is reported by HPET
241 * record in DMAR ACPI table.
242 */
243 if (is_dmar != NULL)
244 *is_dmar = FALSE;
245 src_class = device_get_devclass(src);
246 if (src_class == devclass_find("dmar")) {
247 unit = NULL;
248 if (is_dmar != NULL)
249 *is_dmar = TRUE;
250 } else if (src_class == devclass_find("hpet")) {
251 unit = dmar_find_hpet(src, rid);
252 } else {
253 unit = dmar_find(src, bootverbose);
254 if (unit != NULL && rid != NULL)
255 iommu_get_requester(src, rid);
256 }
257 return (unit);
258 }
259
260 static void
dmar_ir_program_irte(struct dmar_unit * unit,u_int idx,uint64_t low,uint16_t rid)261 dmar_ir_program_irte(struct dmar_unit *unit, u_int idx, uint64_t low,
262 uint16_t rid)
263 {
264 dmar_irte_t *irte;
265 uint64_t high;
266
267 KASSERT(idx < unit->irte_cnt,
268 ("bad cookie %d %d", idx, unit->irte_cnt));
269 irte = &(unit->irt[idx]);
270 high = DMAR_IRTE2_SVT_RID | DMAR_IRTE2_SQ_RID |
271 DMAR_IRTE2_SID_RID(rid);
272 if (bootverbose) {
273 device_printf(unit->dev,
274 "programming irte[%d] rid %#x high %#jx low %#jx\n",
275 idx, rid, (uintmax_t)high, (uintmax_t)low);
276 }
277 DMAR_LOCK(unit);
278 if ((irte->irte1 & DMAR_IRTE1_P) != 0) {
279 /*
280 * The rte is already valid. Assume that the request
281 * is to remap the interrupt for balancing. Only low
282 * word of rte needs to be changed. Assert that the
283 * high word contains expected value.
284 */
285 KASSERT(irte->irte2 == high,
286 ("irte2 mismatch, %jx %jx", (uintmax_t)irte->irte2,
287 (uintmax_t)high));
288 dmar_pte_update(&irte->irte1, low);
289 } else {
290 dmar_pte_store(&irte->irte2, high);
291 dmar_pte_store(&irte->irte1, low);
292 }
293 dmar_qi_invalidate_iec(unit, idx, 1);
294 DMAR_UNLOCK(unit);
295
296 }
297
298 static int
dmar_ir_free_irte(struct dmar_unit * unit,u_int cookie)299 dmar_ir_free_irte(struct dmar_unit *unit, u_int cookie)
300 {
301 dmar_irte_t *irte;
302
303 KASSERT(unit != NULL && unit->ir_enabled,
304 ("unmap: cookie %d unit %p", cookie, unit));
305 KASSERT(cookie < unit->irte_cnt,
306 ("bad cookie %u %u", cookie, unit->irte_cnt));
307 irte = &(unit->irt[cookie]);
308 dmar_pte_clear(&irte->irte1);
309 dmar_pte_clear(&irte->irte2);
310 DMAR_LOCK(unit);
311 dmar_qi_invalidate_iec(unit, cookie, 1);
312 DMAR_UNLOCK(unit);
313 vmem_free(unit->irtids, cookie, 1);
314 return (0);
315 }
316
317 static u_int
clp2(u_int v)318 clp2(u_int v)
319 {
320
321 return (powerof2(v) ? v : 1 << fls(v));
322 }
323
324 int
dmar_init_irt(struct dmar_unit * unit)325 dmar_init_irt(struct dmar_unit *unit)
326 {
327
328 if ((unit->hw_ecap & DMAR_ECAP_IR) == 0)
329 return (0);
330 unit->ir_enabled = 1;
331 TUNABLE_INT_FETCH("hw.dmar.ir", &unit->ir_enabled);
332 if (!unit->ir_enabled)
333 return (0);
334 if (!unit->qi_enabled) {
335 unit->ir_enabled = 0;
336 if (bootverbose)
337 device_printf(unit->dev,
338 "QI disabled, disabling interrupt remapping\n");
339 return (0);
340 }
341 unit->irte_cnt = clp2(num_io_irqs);
342 unit->irt = kmem_alloc_contig(unit->irte_cnt * sizeof(dmar_irte_t),
343 M_ZERO | M_WAITOK, 0, dmar_high, PAGE_SIZE, 0,
344 DMAR_IS_COHERENT(unit) ?
345 VM_MEMATTR_DEFAULT : VM_MEMATTR_UNCACHEABLE);
346 if (unit->irt == NULL)
347 return (ENOMEM);
348 unit->irt_phys = pmap_kextract((vm_offset_t)unit->irt);
349 unit->irtids = vmem_create("dmarirt", 0, unit->irte_cnt, 1, 0,
350 M_FIRSTFIT | M_NOWAIT);
351 DMAR_LOCK(unit);
352 dmar_load_irt_ptr(unit);
353 dmar_qi_invalidate_iec_glob(unit);
354 DMAR_UNLOCK(unit);
355
356 /*
357 * Initialize mappings for already configured interrupt pins.
358 * Required, because otherwise the interrupts fault without
359 * irtes.
360 */
361 intr_reprogram();
362
363 DMAR_LOCK(unit);
364 dmar_enable_ir(unit);
365 DMAR_UNLOCK(unit);
366 return (0);
367 }
368
369 void
dmar_fini_irt(struct dmar_unit * unit)370 dmar_fini_irt(struct dmar_unit *unit)
371 {
372
373 unit->ir_enabled = 0;
374 if (unit->irt != NULL) {
375 dmar_disable_ir(unit);
376 dmar_qi_invalidate_iec_glob(unit);
377 vmem_destroy(unit->irtids);
378 kmem_free(unit->irt, unit->irte_cnt * sizeof(dmar_irte_t));
379 }
380 }
381