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Searched refs:isBeforeLegalize (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1510 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine()
1526 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine()
1686 if (!DCI.isBeforeLegalize() || in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp617 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedBits()
633 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedBits()
2941 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedVectorElts()
4208 !DCI.isBeforeLegalize()); in foldSetCCWithBinOp()
4503 DCI.isBeforeLegalize() && N0->hasOneUse()) { in SimplifySetCC()
4590 if (DCI.isBeforeLegalize() && in SimplifySetCC()
5042 getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); in SimplifySetCC()
5068 EVT ShiftTy = getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); in SimplifySetCC()
6575 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout(), !DCI.isBeforeLegalize()); in prepareUREMEqFold()
6824 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout(), !DCI.isBeforeLegalize()); in prepareSREMEqFold()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2796 if (DCI.isBeforeLegalize() && VT.isScalarInteger() && in performBitcastCombine()
2831 if (DCI.isBeforeLegalize() && VT.isScalarInteger() && in performSETCCCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp3748 if (!DCI.isBeforeLegalize()) in performLoadCombine()
3801 if (!DCI.isBeforeLegalize()) in performStoreCombine()
5176 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine()
H A DSIISelLowering.cpp11317 if (DCI.isBeforeLegalize()) in performAndCombine()
13100 if (Vec.hasOneUse() && DCI.isBeforeLegalize() && VecEltVT == ResVT) { in performExtractVectorEltCombine()
13151 if (!DCI.isBeforeLegalize()) in performExtractVectorEltCombine()
14477 if (!DCI.isBeforeLegalize()) { in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4092 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; } in isBeforeLegalize() function
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp17832 if (!DCI.isBeforeLegalize() && in performANDSETCCCombine()
17986 if (!Subtarget->hasSVE() || DCI.isBeforeLegalize()) in performFirstTrueTestVectorCombine()
18016 if (!Subtarget->hasSVE() || DCI.isBeforeLegalize()) in performLastTrueTestVectorCombine()
19777 if (DCI.isBeforeLegalize()) in tryConvertSVEWideCompare()
21225 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in performTBISimplification()
21718 if (!DCI.isBeforeLegalize()) in performMaskedGatherScatterCombine()
21754 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in performNEONPostLDSTCombine()
22430 if (DCI.isBeforeLegalize() && in performVecReduceBitwiseCombine()
22492 if (DCI.isBeforeLegalize() && VT.isScalarInteger() && in performSETCCCombine()
22883 assert(DCI.isBeforeLegalize() || in performSelectCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp12711 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() in AddCombineBUILD_VECTORToVPADDL()
13531 if (DCI.isBeforeLegalize()) return SDValue(); in PerformADDECombine()
13913 if (DCI.isBeforeLegalize()) in PerformSHLSimplify()
14221 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformMULCombine()
14299 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in CombineANDShift()
16234 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformVLDCombine()
16242 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformMVEVLDCombine()
17707 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformShiftCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp42885 if (DCI.isBeforeLegalize()) { in combineBitcast()
45261 if (DCI.isBeforeLegalize() || TLI.isTypeLegal(IntVT)) { in combineSelect()
45288 if (DCI.isBeforeLegalize() && !Subtarget.hasAVX512() && in combineSelect()
46246 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) { in combineCMov()
46759 if (DCI.isBeforeLegalize() && VT.isVector()) in combineMul()
46771 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in combineMul()
50001 RegVT.getScalarType() == MVT::i1 && DCI.isBeforeLegalize()) { in combineLoad()
51888 (DCI.isBeforeLegalize() || in combineBITREVERSE()
52985 isa<ConstantSDNode>(RHS) && !DCI.isBeforeLegalize()) { in combineSetCC()
53332 if (DCI.isBeforeLegalize()) { in combineGatherScatter()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp14844 if (Subtarget.hasP9Altivec() && !DCI.isBeforeLegalize()) { in DAGCombineBuildVector()
15701 if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() && in PerformDAGCombine()
16151 if (!DCI.isBeforeLegalize() || !Is64BitBswapOn64BitTgt || in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp15022 if (!DCI.isBeforeLegalize()) in legalizeScatterGatherIndexType()
15816 if (DCI.isBeforeLegalize() && IsScalarizable && in PerformDAGCombine()
15845 L && DCI.isBeforeLegalize() && IsScalarizable && L->isSimple() && in PerformDAGCombine()