/freebsd/sys/dev/liquidio/base/ |
H A D | cn23xx_pf_device.c | 150 reg_val = in lio_cn23xx_pf_setup_global_mac_regs() 157 reg_val = reg_val | in lio_cn23xx_pf_setup_global_mac_regs() 162 reg_val); in lio_cn23xx_pf_setup_global_mac_regs() 217 reg_val); in lio_cn23xx_pf_reset_io_queues() 261 reg_val); in lio_cn23xx_pf_setup_global_input_regs() 277 reg_val = in lio_cn23xx_pf_setup_global_input_regs() 283 reg_val); in lio_cn23xx_pf_setup_global_input_regs() 351 reg_val); in lio_cn23xx_pf_setup_global_output_regs() 476 reg_val = in lio_cn23xx_pf_setup_oq_regs() 486 reg_val = in lio_cn23xx_pf_setup_oq_regs() [all …]
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/freebsd/sys/arm/qualcomm/ |
H A D | qcom_cpu_kpssv2.c | 81 uint32_t reg_val; in qcom_cpu_kpssv2_regulator_start() local 138 reg_val = (64 << QCOM_APC_PWR_GATE_CTL_BHS_CNT_SHIFT) in qcom_cpu_kpssv2_regulator_start() 141 bus_space_write_4(acc_tag, acc_handle, QCOM_APC_PWR_GATE_CTL, reg_val); in qcom_cpu_kpssv2_regulator_start() 149 reg_val |= 0x3f << QCOM_APC_PWR_GATE_CTL_BHS_SEG_SHIFT; in qcom_cpu_kpssv2_regulator_start() 150 bus_space_write_4(acc_tag, acc_handle, QCOM_APC_PWR_GATE_CTL, reg_val); in qcom_cpu_kpssv2_regulator_start() 158 reg_val |= 0x3f << QCOM_APC_PWR_GATE_CTL_LDO_BYP_SHIFT; in qcom_cpu_kpssv2_regulator_start() 159 bus_space_write_4(acc_tag, acc_handle, QCOM_APC_PWR_GATE_CTL, reg_val); in qcom_cpu_kpssv2_regulator_start() 172 reg_val = QCOM_APCS_CPU_PWR_CTL_COREPOR_RST in qcom_cpu_kpssv2_regulator_start() 181 reg_val &= ~QCOM_APCS_CPU_PWR_CTL_CLAMP; in qcom_cpu_kpssv2_regulator_start() 189 reg_val &= ~QCOM_APCS_CPU_PWR_CTL_COREPOR_RST; in qcom_cpu_kpssv2_regulator_start() [all …]
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/freebsd/sys/arm/allwinner/ |
H A D | if_emac.c | 369 len = reg_val & 0xffff; in emac_rxeof() 502 uint32_t reg_val; in emac_init_locked() local 525 reg_val |= (0xd << 2); in emac_init_locked() 539 reg_val |= EMAC_TX_AB_M; in emac_init_locked() 540 reg_val &= EMAC_TX_TM; in emac_init_locked() 546 reg_val &= EMAC_RX_TM; in emac_init_locked() 584 reg_val |= EMAC_INT_EN; in emac_init_locked() 676 uint32_t reg_val; in emac_stop_locked() local 702 uint32_t reg_val; in emac_intr() local 728 reg_val |= EMAC_INT_EN; in emac_intr() [all …]
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/freebsd/sys/arm/ti/ |
H A D | ti_pinmux.c | 133 uint16_t reg_val; in ti_pinmux_padconf_set_internal() local 157 reg_val, muxmode); in ti_pinmux_padconf_set_internal() 159 ti_pinmux_write_2(sc, padconf->reg_off, reg_val); in ti_pinmux_padconf_set_internal() 213 uint16_t reg_val; in ti_pinmux_padconf_get() local 224 reg_val = ti_pinmux_read_2(ti_pinmux_sc, padconf->reg_off); in ti_pinmux_padconf_get() 228 *state = (reg_val & ti_pinmux_dev->padconf_sate_mask); in ti_pinmux_padconf_get() 255 uint16_t reg_val; in ti_pinmux_padconf_set_gpiomode() local 277 ti_pinmux_write_2(ti_pinmux_sc, padconf->reg_off, reg_val); in ti_pinmux_padconf_set_gpiomode() 300 uint16_t reg_val; in ti_pinmux_padconf_get_gpiomode() local 316 reg_val = ti_pinmux_read_2(ti_pinmux_sc, padconf->reg_off); in ti_pinmux_padconf_get_gpiomode() [all …]
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/freebsd/sys/contrib/dev/athk/ath10k/ |
H A D | hw.c | 747 u32 addr, reg_val, mem_val; in ath10k_hw_qca6174_enable_pll_clock() local 793 reg_val &= ~WLAN_PLL_SETTLE_TIME_MASK; in ath10k_hw_qca6174_enable_pll_clock() 805 reg_val &= ~SOC_CORE_CLK_CTRL_DIV_MASK; in ath10k_hw_qca6174_enable_pll_clock() 806 reg_val |= SM(1, SOC_CORE_CLK_CTRL_DIV); in ath10k_hw_qca6174_enable_pll_clock() 851 if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING)) in ath10k_hw_qca6174_enable_pll_clock() 860 reg_val &= ~WLAN_PLL_CONTROL_BYPASS_MASK; in ath10k_hw_qca6174_enable_pll_clock() 861 reg_val |= SM(0, WLAN_PLL_CONTROL_BYPASS); in ath10k_hw_qca6174_enable_pll_clock() 882 if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING)) in ath10k_hw_qca6174_enable_pll_clock() 891 reg_val &= ~SOC_CPU_CLOCK_STANDARD_MASK; in ath10k_hw_qca6174_enable_pll_clock() 892 reg_val |= SM(1, SOC_CPU_CLOCK_STANDARD); in ath10k_hw_qca6174_enable_pll_clock() [all …]
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H A D | bmi.c | 199 int ath10k_bmi_write_soc_reg(struct ath10k *ar, u32 address, u32 reg_val) in ath10k_bmi_write_soc_reg() argument 207 address, reg_val); in ath10k_bmi_write_soc_reg() 216 cmd.write_soc_reg.value = __cpu_to_le32(reg_val); in ath10k_bmi_write_soc_reg() 228 int ath10k_bmi_read_soc_reg(struct ath10k *ar, u32 address, u32 *reg_val) in ath10k_bmi_read_soc_reg() argument 254 *reg_val = __le32_to_cpu(resp.read_soc_reg.value); in ath10k_bmi_read_soc_reg() 257 *reg_val); in ath10k_bmi_read_soc_reg()
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/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/ |
H A D | adf_c4xxx_ras.c | 919 u32 reg_val = 0; in adf_handle_parser_uerr() local 927 reg_val); in adf_handle_parser_uerr() 946 u64 reg_val; in adf_handle_mac_intr() local 957 if (reg_val & ADF_C4XXX_MAC_ERROR_TX_FCS) in adf_handle_mac_intr() 1006 if (reg_val & ADF_C4XXX_MAC_ERROR_RX_FCS) in adf_handle_mac_intr() 1027 if (reg_val & ADF_C4XXX_MAC_RX_LINK_UP) in adf_handle_mac_intr() 1072 u32 reg_val; in adf_handle_rf_par_err() local 1079 intr_status = reg_val & rf_par_msk; in adf_handle_rf_par_err() 1185 u32 reg_val; in adf_handle_congest_mngt_intr() local 1187 reg_val = ADF_CSR_RD(aram_base_addr, in adf_handle_congest_mngt_intr() [all …]
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/freebsd/sys/dev/qlnx/qlnxe/ |
H A D | ecore_init_fw_funcs.c | 658 u32 reg_val, i; in ecore_poll_on_qm_cmd_ready() local 660 for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && !reg_val; i++) { in ecore_poll_on_qm_cmd_ready() 1290 u32 reg_val; in ecore_set_vxlan_enable() local 1321 u32 reg_val; in ecore_set_gre_enable() local 1370 u32 reg_val; in ecore_set_geneve_enable() local 1408 u32 reg_val, cfg_mask; in ecore_set_vxlan_no_l2_enable() local 1419 reg_val |= cfg_mask; in ecore_set_vxlan_no_l2_enable() 1427 reg_val &= ~cfg_mask; in ecore_set_vxlan_no_l2_enable() 1791 u32 * reg_val; in ecore_update_eth_rss_ind_table_entry() local 1820 reg_val = (u32*)rss_ind_mask; in ecore_update_eth_rss_ind_table_entry() [all …]
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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
H A D | ar9300_gpio.c | 429 u_int32_t reg_val; in ar9300_gpio_set_intr() local 463 reg_val = OS_REG_READ(ah, regs[i]); in ar9300_gpio_set_intr() 465 reg_val &= ~(1 << reg_bit); in ar9300_gpio_set_intr() 466 OS_REG_WRITE(ah, regs[i], reg_val); in ar9300_gpio_set_intr() 470 field_val = (reg_val >> shifts[i]) & gpio_mask; in ar9300_gpio_set_intr() 481 reg_val &= ~(1 << reg_bit); in ar9300_gpio_set_intr() 484 reg_val |= (1 << reg_bit); in ar9300_gpio_set_intr() 490 reg_val = OS_REG_READ(ah, regs[i]); in ar9300_gpio_set_intr() 492 reg_val |= (1 << reg_bit); in ar9300_gpio_set_intr() 493 OS_REG_WRITE(ah, regs[i], reg_val); in ar9300_gpio_set_intr() [all …]
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H A D | ar9300_reset.c | 3255 u_int32_t reg_val; 3276 reg_val &= 0xfffffffd; 3281 reg_val &= 0xfffff7ff; 3301 reg_val = ((reg_val & 0xe3ffffff) | (reflo << 26)); 3337 reg_val &= 0xfc0fffff; 3340 reg_val &= 0xfdffffff; 3348 reg_val = reg_val | (0x1 << (19 + i)) | ((offs_6_1) << 20); 3356 reg_val = reg_val | ((offs_6_1 - 1) << 20); 3362 reg_val = reg_val | (0x1 << 25); 3370 reg_val = reg_val | (offs_0 << 25); [all …]
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H A D | ar9300_recv.c | 283 u_int32_t reg_val = 0; in ar9300_promisc_mode() local 284 reg_val = OS_REG_READ(ah, AR_RX_FILTER); in ar9300_promisc_mode() 286 reg_val |= AR_RX_PROM; in ar9300_promisc_mode() 288 reg_val &= ~AR_RX_PROM; in ar9300_promisc_mode() 290 OS_REG_WRITE(ah, AR_RX_FILTER, reg_val); in ar9300_promisc_mode()
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/freebsd/sys/dev/ixgbe/ |
H A D | ixgbe_x550.c | 2155 u32 reg_val; in ixgbe_setup_kr_speed_x550em() local 2635 u16 reg_slice, reg_val; in ixgbe_setup_mac_link_sfp_x550em() local 2663 reg_val); in ixgbe_setup_mac_link_sfp_x550em() 2679 u32 reg_val; in ixgbe_setup_sfi_x550a() local 2708 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); in ixgbe_setup_sfi_x550a() 2831 u32 reg_val; in ixgbe_setup_ixfi_x550em_x() local 2842 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); in ixgbe_setup_ixfi_x550em_x() 2857 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); in ixgbe_setup_ixfi_x550em_x() 2902 u32 reg_val; in ixgbe_setup_ixfi_x550em() local 3060 u32 reg_val; in ixgbe_setup_phy_loopback_x550em() local [all …]
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H A D | ixgbe_82599.h | 63 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val); 64 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 reg_val, bool locked);
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/freebsd/sys/dev/axgbe/ |
H A D | xgbe-common.h | 1518 SET_BITS(reg_val, \ 1521 XGMAC_IOWRITE((_pdata), _reg, reg_val); \ 1544 SET_BITS(reg_val, \ 1569 SET_BITS(reg_val, \ 1627 SET_BITS(reg_val, \ 1630 XSIR0_IOWRITE((_pdata), _reg, reg_val); \ 1647 SET_BITS(reg_val, \ 1670 SET_BITS(reg_val, \ 1704 SET_BITS(reg_val, \ 1707 XP_IOWRITE((_pdata), (_reg), reg_val); \ [all …]
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H A D | xgbe-dev.c | 491 unsigned int reg, reg_val; in xgbe_disable_tx_flow_control() local 517 unsigned int reg, reg_val; in xgbe_enable_tx_flow_control() local 1244 reg_val |= (1 << port); in xgbe_set_ext_mii_mode() 1957 unsigned int i, j, reg, reg_val; in xgbe_config_queue_mapping() local 1987 reg_val = 0; in xgbe_config_queue_mapping() 2009 reg_val = 0; in xgbe_config_queue_mapping() 2014 reg_val = 0; in xgbe_config_queue_mapping() 2024 reg_val = 0; in xgbe_config_queue_mapping() 2607 unsigned int reg_val, i; in xgbe_enable_rx() local 2618 reg_val = 0; in xgbe_enable_rx() [all …]
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/freebsd/sys/dev/qat/qat_common/ |
H A D | adf_aer.c | 55 unsigned int aer_offset, reg_val = 0; in adf_aer_store_ppaerucm_reg() local 61 reg_val = in adf_aer_store_ppaerucm_reg() 64 hw_data->aerucm_mask = reg_val; in adf_aer_store_ppaerucm_reg() 128 u32 aer_offset, reg_val = 0; in adf_dev_pre_reset() local 131 reg_val = in adf_dev_pre_reset() 133 reg_val |= ADF_PPAERUCM_MASK; in adf_dev_pre_reset() 136 reg_val, in adf_dev_pre_reset()
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/freebsd/sys/dev/bxe/ |
H A D | ecore_init.h | 747 uint32_t reg_val; in ecore_set_mcp_parity() local 750 reg_val = REG_RD(sc, mcp_attn_ctl_regs[i].addr); in ecore_set_mcp_parity() 753 reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */ in ecore_set_mcp_parity() 757 REG_WR(sc, mcp_attn_ctl_regs[i].addr, reg_val); in ecore_set_mcp_parity() 799 uint32_t reg_val, mcp_aeu_bits = in ecore_clear_blocks_parity() local 815 reg_val = REG_RD(sc, ecore_blocks_parity_data[i]. in ecore_clear_blocks_parity() 817 if (reg_val & reg_mask) in ecore_clear_blocks_parity() 821 reg_val & reg_mask); in ecore_clear_blocks_parity() 826 reg_val = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_MCP); in ecore_clear_blocks_parity() 827 if (reg_val & mcp_aeu_bits) in ecore_clear_blocks_parity() [all …]
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/freebsd/sys/dev/vnic/ |
H A D | nicvf_queues.c | 126 uint64_t reg_val; in nicvf_poll_reg() local 134 if (((reg_val & bit_mask) >> bit_pos) == val) in nicvf_poll_reg() 2049 uint64_t reg_val; in nicvf_enable_intr() local 2070 reg_val |= (1UL << NICVF_INTR_MBOX_SHIFT); in nicvf_enable_intr() 2088 uint64_t reg_val = 0; in nicvf_disable_intr() local 2107 reg_val |= (1UL << NICVF_INTR_MBOX_SHIFT); in nicvf_disable_intr() 2125 uint64_t reg_val = 0; in nicvf_clear_intr() local 2144 reg_val = (1UL << NICVF_INTR_MBOX_SHIFT); in nicvf_clear_intr() 2155 nicvf_reg_write(nic, NIC_VF_INT, reg_val); in nicvf_clear_intr() 2162 uint64_t reg_val; in nicvf_is_intr_enabled() local [all …]
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/freebsd/contrib/llvm-project/lldb/source/Core/ |
H A D | DumpRegisterValue.cpp | 60 void lldb_private::DumpRegisterValue(const RegisterValue ®_val, Stream &s, in DumpRegisterValue() argument 68 if (!reg_val.GetData(data)) in DumpRegisterValue() 134 dump_type_value(fields_type, reg_val.GetAsUInt32(), exe_scope, reg_info, in DumpRegisterValue() 137 dump_type_value(fields_type, reg_val.GetAsUInt64(), exe_scope, reg_info, in DumpRegisterValue()
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/freebsd/sys/dev/qat/qat_hw/qat_200xx/ |
H A D | adf_drv.c | 86 unsigned int i = 0, bar_nr = 0, reg_val = 0; in adf_attach() local 135 reg_val = pci_read_config(dev, ADF_200XX_PFIEERRUNCSTSR, 4); in adf_attach() 136 if (reg_val) { in adf_attach() 140 reg_val); in adf_attach() 141 pci_write_config(dev, ADF_200XX_PFIEERRUNCSTSR, reg_val, 4); in adf_attach()
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/freebsd/sys/dev/mge/ |
H A D | if_mge.c | 456 uint32_t reg_idx, reg_off, reg_val, i; in mge_set_ucast_address() local 461 reg_val = (1 | (queue << 1)) << reg_off; in mge_set_ucast_address() 475 uint32_t reg_val, i; in mge_set_prom_mode() local 1086 volatile uint32_t reg_val; in mge_init_locked() local 1176 reg_val |= PORT_SERIAL_ENABLE; in mge_init_locked() 1180 reg_val = MGE_READ(sc, MGE_PORT_STATUS); in mge_init_locked() 1181 if (reg_val & MGE_STATUS_LINKUP) in mge_init_locked() 1750 uint32_t reg_val, queued = 0; in mge_start_locked() local 1809 volatile uint32_t reg_val, status; in mge_stop() local 1830 reg_val = MGE_READ(sc, MGE_TX_QUEUE_CMD); in mge_stop() [all …]
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/freebsd/sys/dev/cxgb/common/ |
H A D | cxgb_ael1002.c | 90 struct reg_val { struct 526 static struct reg_val regs[] = { in ael2005_setup_sr_edc() 823 static struct reg_val regs[] = { in ael2005_setup_twinax_edc() 827 static struct reg_val preemphasis[] = { in ael2005_setup_twinax_edc() 1253 static struct reg_val regs0[] = { in ael2005_reset() 1263 static struct reg_val regs1[] = { in ael2005_reset() 1408 static struct reg_val regs[] = { in ael2020_setup_sr_edc() 1434 static struct reg_val uCclock40MHz[] = { in ael2020_setup_twinax_edc() 1445 static struct reg_val uCactivate[] = { in ael2020_setup_twinax_edc() 1940 struct reg_val regs[] = { in ael2020_intr_enable() [all …]
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/freebsd/sys/arm/mv/ |
H A D | gpio.c | 882 uint32_t reg_val; in mv_gpio_reg_set() local 884 reg_val = mv_gpio_reg_read(dev, reg); in mv_gpio_reg_set() 885 reg_val |= GPIO(pin); in mv_gpio_reg_set() 886 mv_gpio_reg_write(dev, reg, reg_val); in mv_gpio_reg_set() 892 uint32_t reg_val; in mv_gpio_reg_clear() local 894 reg_val = mv_gpio_reg_read(dev, reg); in mv_gpio_reg_clear() 895 reg_val &= ~(GPIO(pin)); in mv_gpio_reg_clear() 896 mv_gpio_reg_write(dev, reg, reg_val); in mv_gpio_reg_clear() 938 uint32_t reg, reg_val; in mv_gpio_polarity() local 949 if (reg_val) in mv_gpio_polarity() [all …]
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/freebsd/sys/dev/etherswitch/ar40xx/ |
H A D | ar40xx_hw_mdio.c | 92 uint16_t mmd_num, uint16_t reg_id, uint16_t reg_val) in ar40xx_hw_phy_mmd_write() argument 104 reg_val); in ar40xx_hw_phy_mmd_write()
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/freebsd/sys/dev/e1000/ |
H A D | e1000_i210.c | 711 u32 wuc, mdicnfg, ctrl, ctrl_ext, reg_val; in e1000_pll_workaround_i210() local 720 reg_val = mdicnfg & ~E1000_MDICNFG_EXT_MDIO; in e1000_pll_workaround_i210() 721 E1000_WRITE_REG(hw, E1000_MDICNFG, reg_val); in e1000_pll_workaround_i210() 753 reg_val = (E1000_INVM_AUTOLOAD << 4) | (tmp_nvm << 16); in e1000_pll_workaround_i210() 754 E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val); in e1000_pll_workaround_i210() 762 reg_val = (E1000_INVM_AUTOLOAD << 4) | (nvm_word << 16); in e1000_pll_workaround_i210() 763 E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val); in e1000_pll_workaround_i210()
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