/freebsd/contrib/llvm-project/libunwind/src/ |
H A D | CompactUnwinder.hpp | 114 frameUnwind(addressSpace, registers); in stepWithCompactEncodingEBPFrame() 244 registers.setSP((uint32_t)bp + 8); in frameUnwind() 252 Registers_x86 ®isters) { in framelessUnwind() argument 471 uint64_t rbp = registers.getRBP(); in frameUnwind() 475 registers.setSP(rbp + 16); in frameUnwind() 534 Registers_arm64 ®isters) { in stepWithCompactEncodingFrameless() argument 605 registers.setSP(savedRegisterLoc); in stepWithCompactEncodingFrameless() 608 registers.setIP(registers.getRegister(UNW_AARCH64_LR)); in stepWithCompactEncodingFrameless() 616 Registers_arm64 ®isters) { in stepWithCompactEncodingFrame() argument 683 uint64_t fp = registers.getFP(); in stepWithCompactEncodingFrame() [all …]
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H A D | DwarfInstructions.hpp | 66 const R ®isters) { in getCFA() argument 72 registers, 0); in getCFA() 100 getSparcWCookie(registers, 0)); in getSavedRegister() 108 registers, cfa); in getSavedRegister() 132 registers, cfa)); in getSavedFloatRegister() 158 registers, cfa)); in getSavedVectorRegister() 206 pint_t sp = registers.getSP(); in stepWithDwarf() 233 R newRegisters = registers; in stepWithDwarf() 254 if (registers.validFloatRegister(i)) in stepWithDwarf() 265 else if (registers.validRegister(i)) in stepWithDwarf() [all …]
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/freebsd/sys/arm/arm/ |
H A D | db_trace.c | 81 state->registers[LR]); in db_stack_trace_cmd() 82 db_printsym(state->registers[LR], DB_STGY_PROC); in db_stack_trace_cmd() 85 state->registers[SP], state->registers[FP]); in db_stack_trace_cmd() 95 state->registers[reg]); in db_stack_trace_cmd() 118 if (state->registers[PC] < VM_MIN_KERNEL_ADDRESS) { in db_stack_trace_cmd() 144 state.registers[FP] = ctx->pcb_regs.sf_r11; in db_trace_thread() 145 state.registers[SP] = ctx->pcb_regs.sf_sp; in db_trace_thread() 146 state.registers[LR] = ctx->pcb_regs.sf_lr; in db_trace_thread() 147 state.registers[PC] = ctx->pcb_regs.sf_pc; in db_trace_thread() 165 state.registers[SP] = sp; in db_trace_self() [all …]
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H A D | stack_machdep.c | 44 if (stack_put(st, state->registers[PC]) == -1) in stack_capture() 58 state.registers[FP] = (uint32_t)__builtin_frame_address(0); in stack_save() 59 state.registers[SP] = sp; in stack_save() 60 state.registers[LR] = (uint32_t)__builtin_return_address(0); in stack_save() 61 state.registers[PC] = (uint32_t)stack_save; in stack_save() 78 state.registers[FP] = td->td_pcb->pcb_regs.sf_r11; in stack_save_td() 79 state.registers[SP] = td->td_pcb->pcb_regs.sf_sp; in stack_save_td() 80 state.registers[LR] = td->td_pcb->pcb_regs.sf_lr; in stack_save_td() 81 state.registers[PC] = td->td_pcb->pcb_regs.sf_pc; in stack_save_td()
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H A D | unwind.c | 413 state->registers[reg] = *vsp++; in unwind_exec_insn() 426 state->registers[SP] = in unwind_exec_insn() 446 state->registers[reg] = *vsp++; in unwind_exec_insn() 454 state->registers[14] = *vsp++; in unwind_exec_insn() 480 state->registers[reg] = *vsp++; in unwind_exec_insn() 502 state->registers[SP] = (uint32_t)vsp; in unwind_exec_insn() 507 state->registers[FP], state->registers[SP], state->registers[LR], in unwind_exec_insn() 508 state->registers[PC]); in unwind_exec_insn() 521 state->registers[PC] = 0; in unwind_tab() 547 if (state->registers[PC] == 0) { in unwind_tab() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfoMMA.td | 9 // Register info for registers related to MMA. These are the ACC and UACC 10 // registers. 52 // to assign these registers first. This is done because the ACC registers 53 // must represent 4 advacent vector registers. For example ACC1 must be 57 // We want to allocate these registers even before we allocate 79 // ACC registers. 86 // non-volatile registers. 88 // Placing Altivec registers first and allocate the rest as underlying VSX 91 // paired VSX registers. 102 // the UACC registers. Even global VSRp registers should be allocated after [all …]
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/freebsd/sys/contrib/device-tree/Bindings/usb/ |
H A D | cdns-usb3.txt | 6 - HOST registers area 7 - DEVICE registers area 8 - OTG/DRD registers area 10 "xhci" - for HOST registers space 11 "dev" - for DEVICE registers space 12 "otg" - for OTG/DRD registers space 39 reg = <0xf3000000 0x10000>, /* memory area for HOST registers */ 40 <0xf3010000 0x10000>, /* memory area for DEVICE registers */ 41 <0xf3020000 0x10000>; /* memory area for OTG/DRD registers */
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
H A D | nxp,s32g2-siul2-pinctrl.yaml | 41 - description: MSCR registers group 0 in SIUL2_0 42 - description: MSCR registers group 1 in SIUL2_1 43 - description: MSCR registers group 2 in SIUL2_1 44 - description: IMCR registers group 0 in SIUL2_0 45 - description: IMCR registers group 1 in SIUL2_1 46 - description: IMCR registers group 2 in SIUL2_1 96 /* MSCR0-MSCR101 registers on siul2_0 */ 98 /* MSCR112-MSCR122 registers on siul2_1 */ 100 /* MSCR144-MSCR190 registers on siul2_1 */ 102 /* IMCR0-IMCR83 registers on siul2_0 */ [all …]
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/freebsd/sys/contrib/device-tree/Bindings/i2c/ |
H A D | mellanox,i2c-mlxbf.txt | 7 - reg : address offset and length of the device registers. The 8 registers consist of the following set of resources: 9 1) Smbus block registers. 10 2) Cause master registers. 11 3) Cause slave registers. 12 4) Cause coalesce registers (if compatible isn't set 19 - clock-frequency : bus frequency used to configure timing registers;
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRRegisterInfo.td | 33 // 8-bit general purpose registers 97 // Pseudo registers for unaligned i16 118 // Scratch registers. 120 // Callee saved registers. 124 // Simple lower registers r0..r15 134 // Scratch registers. 136 // Callee saved registers. 139 // Simple lower registers r16..r23 148 // Scratch registers. 186 // Scratch registers. [all …]
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/freebsd/sys/contrib/device-tree/Bindings/display/msm/ |
H A D | gmu.yaml | 97 - description: Core GMU registers 98 - description: GMU PDC registers 99 - description: GMU PDC sequence registers 129 - description: Core GMU registers 131 - description: GMU PDC registers 166 - description: Core GMU registers 167 - description: GMU PDC registers 185 - description: Core GMU registers 187 - description: GMU PDC registers 231 - description: Core GMU registers [all …]
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/freebsd/sys/cddl/dev/dtrace/arm/ |
H A D | dtrace_isa.c | 72 state.registers[FP] = (uint32_t)__builtin_frame_address(0); in dtrace_getpcstack() 73 state.registers[SP] = sp; in dtrace_getpcstack() 74 state.registers[LR] = (uint32_t)__builtin_return_address(0); in dtrace_getpcstack() 75 state.registers[PC] = (uint32_t)dtrace_getpcstack; in dtrace_getpcstack() 90 pcstack[depth++] = state.registers[PC]; in dtrace_getpcstack() 141 state.registers[FP] = (uint32_t)__builtin_frame_address(0); in dtrace_getstackdepth() 142 state.registers[SP] = sp; in dtrace_getstackdepth() 143 state.registers[LR] = (uint32_t)__builtin_return_address(0); in dtrace_getstackdepth() 144 state.registers[PC] = (uint32_t)dtrace_getstackdepth; in dtrace_getstackdepth()
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
H A D | VECallingConv.td | 42 // --> generic 64 bit registers 46 // long double --> pair of generic 64 bit registers 90 // --> generic 64 bit registers 94 // long double --> pair of generic 64 bit registers 105 // vector --> generic vector registers 112 // vector mask --> generic vector mask registers 116 // pair of vector mask --> generic vector mask registers 126 // vector --> generic vector registers 133 // vector mask --> generic vector mask registers 137 // pair of vector mask --> generic vector mask registers [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86RegisterInfo.td | 11 // registers. 40 // which others. We only specify which registers the small registers alias, 49 // 8-bit registers 50 // Low registers 185 // 16-bit registers 233 // 32-bit registers 424 // Tile "registers". 474 // Segment registers 485 // Debug registers 613 // Debug registers. [all …]
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/freebsd/sys/contrib/device-tree/Bindings/mips/ |
H A D | mscc.txt | 14 The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous 20 - reg : Should contain registers location and length 31 The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of 32 the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU 37 - reg : Should contain registers location and length 47 The SoC has a few registers (HSIO) handling miscellaneous functionalities: 53 - reg : Should contain registers location and length
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/freebsd/sys/contrib/device-tree/Bindings/thermal/ |
H A D | rcar-gen3-thermal.yaml | 71 - description: TSC0 registers 72 - description: TSC1 registers 73 - description: TSC2 registers 74 - description: TSC3 registers 75 - description: TSC4 registers 81 - description: TSC1 registers 82 - description: TSC2 registers 83 - description: TSC3 registers 84 - description: TSC4 registers
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/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/gdb-remote/ |
H A D | GDBRemoteRegisterFallback.cpp | 28 std::vector<DynamicRegisterInfo::Register> registers{ in GetRegisters_aarch64() local 36 return registers; in GetRegisters_aarch64() 43 std::vector<DynamicRegisterInfo::Register> registers{ in GetRegisters_msp430() local 48 return registers; in GetRegisters_msp430() 55 std::vector<DynamicRegisterInfo::Register> registers{ in GetRegisters_x86() local 61 return registers; in GetRegisters_x86() 68 std::vector<DynamicRegisterInfo::Register> registers{ in GetRegisters_x86_64() local 75 return registers; in GetRegisters_x86_64()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIRegisterInfo.td | 243 // Aperture registers are 64 bit registers with a LO/HI 32 bit. 295 // Trap handler registers 340 // SGPR registers 348 // VGPR registers 355 // AccVGPR registers 404 // SGPR 32-bit registers 414 // SGPR 64-bit registers 617 // VGPR 32-bit registers 637 // VGPR 64-bit registers 640 // VGPR 96-bit registers [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.td | 33 // of the registers and REGLIST is the list of individual registers. 58 // General-purpose registers 82 // General-purpose registers 158 // Floating-point registers 209 // One of the floating-point registers. 249 // Vector registers 259 // Full vector registers. 286 // All vector registers. 316 // Other registers 332 // Access registers. [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcCallingConv.td | 20 // i32 f32 arguments get passed in integer registers if there is space. 22 // f64 arguments are split and passed through registers or through stack. 52 // array at fixed offsets. Integer arguments are promoted to registers when 57 // to these registers when possible. 61 // promoted to both floating point and integer registers when possible. A 105 // - Promote to integer or floating point registers depending on type. 108 // struct up to 32 bytes in size can be returned in registers. 114 // be assigned to integer and float registers. 121 // arguments whether they are passed in registers or not. 138 // Callee-saved registers are handled by the register window mechanism. [all …]
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/freebsd/sys/contrib/device-tree/Bindings/powerpc/nintendo/ |
H A D | wii.txt | 31 - reg : should contain the VI registers location and length 42 - reg : should contain the PI registers location and length 64 - reg : should contain the DSP registers location and length 76 - reg : should contain the SI registers location and length 87 - reg : should contain the AI registers location and length 97 - reg : should contain the EXI registers location and length 107 - reg : should contain the EHCI registers location and length 117 - reg : should contain the SDHCI registers location and length 126 - reg : should contain the IPC registers location and length 155 - reg : should contain the control registers location and length [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMRegisterInfo.td | 21 // All bits of ARM registers with sub-registers are covered by sub-registers. 78 // Integer registers 101 // Float registers 393 // Condition code registers. 411 // registers (S registers are renamed as portions of D/Q registers). 448 // Allocate non-VFP2 registers D16-D31 first, and prefer even registers on 508 // Pseudo-registers representing odd-even pairs of D registers. The even-odd 548 // Pseudo-registers representing 3 consecutive D registers. 559 // Pseudo 256-bit registers to represent pairs of Q registers. These should 586 // Pseudo 512-bit registers to represent four consecutive Q registers. [all …]
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/freebsd/sys/contrib/device-tree/Bindings/net/ |
H A D | brcm,amac.txt | 9 contains the information of registers in the same order as 11 - reg-names: Names of the registers. 12 "amac_base": Address and length of the GMAC registers 13 "idm_base": Address and length of the GMAC IDM registers 16 registers (required for Northstar2)
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/freebsd/sys/contrib/device-tree/Bindings/mailbox/ |
H A D | microchip,mpfs-mailbox.yaml | 19 - description: mailbox control & data registers 20 - description: mailbox interrupt registers 23 - description: mailbox control registers 24 - description: mailbox interrupt registers 25 - description: mailbox data registers
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/freebsd/sys/contrib/device-tree/Bindings/arm/ |
H A D | atmel-sysregs.txt | 1 Atmel system registers 5 - reg : Should contain registers location and length 9 - reg: Should contain registers location and length 15 - reg: Should contain registers location and length 21 - reg: Should contain registers location and length 35 - reg: Should contain registers location and length 46 - reg: Should contain registers location and length 66 - reg: Should contain registers location and length 85 - reg: Should contain registers location and length
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