Searched refs:scavengeRegisterBackwards (Results 1 – 10 of 10) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.cpp | 101 RS->scavengeRegisterBackwards(XCore::GRRegsRegClass, II, false, 0); in InsertFPConstInst() 174 RS->scavengeRegisterBackwards(XCore::GRRegsRegClass, II, false, 0); in InsertSPConstInst() 180 RS->scavengeRegisterBackwards(XCore::GRRegsRegClass, II, false, 0); in InsertSPConstInst()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | RegisterScavenging.h | 141 Register scavengeRegisterBackwards(const TargetRegisterClass &RC,
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | RegisterScavenging.cpp | 296 Register RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC, in scavengeRegisterBackwards() function in RegScavenger 382 Register SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(), in scavengeVReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIRegisterInfo.cpp | 173 TmpVGPR = RS->scavengeRegisterBackwards(AMDGPU::VGPR_32RegClass, MI, false, in prepare() 203 SavedExecReg = RS->scavengeRegisterBackwards(RC, MI, false, 0, false); in prepare() 1417 SOffset = RS->scavengeRegisterBackwards(AMDGPU::SGPR_32RegClass, MI, false, 0, false); in buildSpillLoadStore() 1438 TmpOffsetVGPR = RS->scavengeRegisterBackwards(AMDGPU::VGPR_32RegClass, MI, false, 0); in buildSpillLoadStore() 1624 TmpOffsetVGPR = RS->scavengeRegisterBackwards(AMDGPU::VGPR_32RegClass, in buildSpillLoadStore() 2349 RS->scavengeRegisterBackwards(*RC, MI, false, 0, !UseSGPR); in eliminateFrameIndex() 2369 : RS->scavengeRegisterBackwards(AMDGPU::SReg_32_XM0RegClass, in eliminateFrameIndex() 2446 : RS->scavengeRegisterBackwards(*RC, MI, false, 0); in eliminateFrameIndex() 2462 Register NewDest = RS->scavengeRegisterBackwards( in eliminateFrameIndex() 2517 Register TmpScaledReg = RS->scavengeRegisterBackwards( in eliminateFrameIndex() [all …]
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H A D | SIInstrInfo.cpp | 711 Register Tmp2 = RS.scavengeRegisterBackwards(AMDGPU::VGPR_32RegClass, MI, in indirectCopyToAGPR() 2915 Scav = RS->scavengeRegisterBackwards( in insertIndirectBranch() 8847 : RS.scavengeRegisterBackwards( in getAddNoCarry()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCRegisterInfo.cpp | 67 RS->scavengeRegisterBackwards(ARC::GPR32RegClass, II, false, SPAdj); in replaceFrameIndex()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiRegisterInfo.cpp | 170 Reg = RS->scavengeRegisterBackwards(Lanai::GPRRegClass, II, false, SPAdj); in eliminateFrameIndex()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVMakeCompressible.cpp | 273 return RS.scavengeRegisterBackwards(*RCToScavenge, FirstMI.getIterator(), in analyzeCompressibleUses()
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H A D | RISCVInstrInfo.cpp | 1127 RS->scavengeRegisterBackwards(RISCV::GPRRegClass, MI.getIterator(), in insertIndirectBranch()
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
H A D | LoongArchInstrInfo.cpp | 444 Register Scav = RS->scavengeRegisterBackwards( in insertIndirectBranch()
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