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Searched refs:BIT2 (Results 1 – 25 of 36) sorted by relevance

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/linux/drivers/scsi/
H A Ddc395x.h74 #define BIT2 0x00000004 macro
81 #define FORMATING_MEDIA BIT2
87 #define ASPI_SUPPORT BIT2
123 #define RESET_DONE BIT2
131 #define OVER_RUN BIT2
141 #define RESET_DEV0 BIT2
167 #define WIDE_NEGO_ENABLE BIT2
594 #define RST_SCSI_BUS BIT2
/linux/drivers/staging/rtl8723bs/include/
H A Drtw_ht.h66 #define LDPC_HT_TEST_TX_ENABLE BIT2
71 #define STBC_HT_TEST_TX_ENABLE BIT2
76 #define BEAMFORMING_HT_BEAMFORMER_TEST BIT2 /* Transmiting Beamforming no matter the target suppo…
H A Dhal_pwr_seq.h48 …AB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW …
105 …K, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1…
183 …_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*Reset CPU*/ \
208 …MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/…
210 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/…
H A Dhal_com_reg.h549 #define RRSR_5_5M BIT2
574 #define HAL92C_WOL_DISASSOC_EVENT BIT2
639 #define BW_OPMODE_20MHZ BIT2
672 #define WOW_MAGIC BIT2 /* Magic packet */
713 #define IMR_VIDOK BIT2 /* AC_VI DMA OK Interrupt */
761 #define RCR_AM BIT2 /* Accept multicast packet */
1280 #define SDIO_HIMR_TXERR_MSK BIT2
1302 #define SDIO_HISR_TXERR BIT2
1375 #define WL_FUNC_EN BIT2 /* WiFi function enable */
H A Drtl8723b_spec.h212 #define IMR_VODOK_8723B BIT2 /* AC_VO DMA OK */
H A Dosdep_service.h19 #define BIT2 0x00000004 macro
/linux/drivers/video/fbdev/via/
H A Ddvi.c335 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
338 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
345 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
370 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
377 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
H A Dlcd.c345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
520 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
561 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
744 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
H A Dshare.h16 #define BIT2 0x04 macro
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h26 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
130 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
199 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
205 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
386 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
523 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
/linux/drivers/staging/rtl8723bs/hal/
H A DHalHWImg8723B_MAC.c20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ in CheckPositive()
60 if ((cond1 & BIT2) != 0) /* ALNA */ in CheckPositive()
H A DHalHWImg8723B_RF.c20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ in CheckPositive()
66 if ((cond1 & BIT2) != 0) /* ALNA */ in CheckPositive()
H A DHalHWImg8723B_BB.c20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ in CheckPositive()
61 if ((cond1 & BIT2) != 0) /* ALNA */ in CheckPositive()
H A DHalBtc8723b2Ant.h13 #define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
H A DHalBtc8723b1Ant.h13 #define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2
H A DHal8723BReg.h401 #define IMR_VODOK_8723B BIT2 /* AC_VO DMA OK */
/linux/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbt_precomp.h33 #define BIT2 0x00000004 macro
H A Dhalbtcoutsrc.h89 #define INTF_NOTIFY BIT2
94 #define ALGO_BT_MONITOR BIT2
106 #define WIFI_HS_CONNECTED BIT2
H A Dhalbtc8192e2ant.h12 #define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT2
H A Dhalbtc8821a1ant.h13 #define BT_INFO_8821A_1ANT_B_INQ_PAGE BIT2
H A Dhalbtc8821a2ant.h13 #define BT_INFO_8821A_2ANT_B_INQ_PAGE BIT2
H A Dhalbtc8723b2ant.h15 #define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
H A Dhalbtc8723b1ant.h12 #define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2
/linux/drivers/tty/
H A Dsynclink_gt.c191 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
1933 if (status & BIT2) { in cts_change()
3899 wr_reg32(info, RDCSR, (BIT2 + BIT0)); in rx_start()
3902 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); in rx_start()
3948 wr_reg32(info, TDCSR, BIT2 + BIT0); in tx_start()
4168 val = BIT2; in sync_mode()
4305 val |= BIT2; /* 001, rxclk = TXC Input */ in sync_mode()
4416 if (status & BIT2) in get_gtsignals()
4458 val |= BIT2; in msc_set_vcr()
4477 val |= BIT2; in set_gtsignals()
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/linux/include/uapi/linux/
H A Dsynclink.h21 #define BIT2 0x0004 macro

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