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Searched refs:BIT4 (Results 1 – 25 of 39) sorted by relevance

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/linux/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h54 …MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disabl…
83 …PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x0…
85 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b…
87 …FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:1…
98 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] …
107 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b…
118 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] …
126 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b…
161 …{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4…
191 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*switch TSF to…
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H A Dhal_com_reg.h551 #define RRSR_6M BIT4
576 #define HAL92C_WOL_FW_DISCONNECT_EVENT BIT4
711 #define IMR_BKDOK BIT4 /* AC_BK DMA OK Interrupt */
759 #define RCR_ADD3 BIT4 /* Accept address 3 match packet */
1282 #define SDIO_HIMR_TXFOVW_MSK BIT4
1304 #define SDIO_HISR_TXFOVW BIT4
H A Drtl8723b_spec.h210 #define IMR_BEDOK_8723B BIT4 /* AC_BE DMA OK */
H A Dosdep_service.h21 #define BIT4 0x00000010 macro
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h99 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
279 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
375 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
416 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
475 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
482 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
488 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \
508 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
529 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
555 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
[all …]
/linux/drivers/scsi/
H A Ddc395x.h72 #define BIT4 0x00000010 macro
133 #define PARITY_ERROR BIT4
140 #define ENABLE_TIMER BIT4
169 #define WIDE_NEGO_STATE BIT4
596 #define NO_SEEK BIT4
/linux/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbt_precomp.h35 #define BIT4 0x00000010 macro
H A Dhalbtc8192e2ant.h10 #define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT4
H A Dhalbtc8821a1ant.h11 #define BT_INFO_8821A_1ANT_B_SCO_BUSY BIT4
H A Dhalbtc8821a2ant.h11 #define BT_INFO_8821A_2ANT_B_SCO_BUSY BIT4
H A Dhalbtc8723b2ant.h13 #define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT4
H A Dhalbtc8723b1ant.h10 #define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT4
H A Dhalbtcoutsrc.h96 #define ALGO_TRACE_FW BIT4
108 #define WIFI_P2P_GC_CONNECTED BIT4
/linux/drivers/video/fbdev/via/
H A Ddvi.c61 viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 + in viafb_tmds_trasmitter_identify()
326 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4); in dvi_patch_skew_dvp0()
347 viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4); in dvi_patch_skew_dvp0()
H A Dhw.c947 viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4); in load_fix_bit_crtc_reg()
1713 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1717 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); in set_display_channel()
1720 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); in set_display_channel()
1725 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1728 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); in set_display_channel()
2061 BIT4); in viafb_set_dpa_gfx()
H A Dshare.h18 #define BIT4 0x10 macro
/linux/drivers/staging/rtl8723bs/hal/
H A DHalHWImg8723B_MAC.c16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ in CheckPositive()
H A DHalBtc8723b2Ant.h11 #define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT4
H A DHalBtc8723b1Ant.h11 #define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT4
H A DHalHWImg8723B_RF.c16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ in CheckPositive()
H A DHalHWImg8723B_BB.c16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ in CheckPositive()
H A DHal8723BReg.h399 #define IMR_BEDOK_8723B BIT4 /* AC_BE DMA OK */
/linux/include/uapi/linux/
H A Dsynclink.h23 #define BIT4 0x0010 macro
/linux/drivers/tty/
H A Dsynclink_gt.c353 #define MASK_OVERRUN BIT4
391 #define IRQ_RI BIT4
2133 if (status & (BIT5 + BIT4)) { in isr_rdma()
2158 if (status & (BIT5 + BIT4 + BIT3)) { in isr_tdma()
4038 case 6: val |= BIT4; break; in async_mode()
4040 case 8: val |= BIT5 + BIT4; break; in async_mode()
4078 case 6: val |= BIT4; break; in async_mode()
4080 case 8: val |= BIT5 + BIT4; break; in async_mode()
4303 val |= BIT4; /* 100, rxclk = DPLL */ in sync_mode()
4381 tcr &= ~(BIT5 + BIT4); in tx_set_idle()
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/linux/lib/zstd/common/
H A Dzstd_internal.h69 #define BIT4 16 macro

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