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Searched refs:SSPP_VIG2 (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_top.c96 status->sspp[SSPP_VIG2] = (value >> 8) & 0x3; in dpu_hw_get_danger_status()
208 status->sspp[SSPP_VIG2] = (value >> 8) & 0x1; in dpu_hw_get_safe_status()
H A Ddpu_hw_mdss.h89 SSPP_VIG2, enumerator
H A Ddpu_hw_ctl.c188 case SSPP_VIG2: in dpu_hw_ctl_update_pending_flush_sspp()
464 [SSPP_VIG2] = { { 0, 6, 4 }, { 3, 8 } },
/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_cfg.c28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
198 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
287 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
539 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
H A Dmdp5_ctl.c294 case SSPP_VIG2: return MDP5_CTL_LAYER_REG_VIG2(stage); in mdp_ctl_blend_mask()
317 case SSPP_VIG2: return MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3; in mdp_ctl_blend_ext_mask()
445 case SSPP_VIG2: return MDP5_CTL_FLUSH_VIG2; in mdp_ctl_flush_mask_pipe()
H A Dmdp5_kms.c607 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, in hwpipe_init() enumerator
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_3_0_msm8998.h85 .name = "sspp_2", .id = SSPP_VIG2,
H A Ddpu_4_0_sdm845.h83 .name = "sspp_2", .id = SSPP_VIG2,
H A Ddpu_5_0_sm8150.h92 .name = "sspp_2", .id = SSPP_VIG2,
H A Ddpu_5_1_sc8180x.h91 .name = "sspp_2", .id = SSPP_VIG2,
H A Ddpu_6_0_sm8250.h91 .name = "sspp_2", .id = SSPP_VIG2,
H A Ddpu_7_0_sm8350.h91 .name = "sspp_2", .id = SSPP_VIG2,
H A Ddpu_9_0_sm8550.h81 .name = "sspp_2", .id = SSPP_VIG2,
H A Ddpu_8_1_sm8450.h92 .name = "sspp_2", .id = SSPP_VIG2,
H A Ddpu_10_0_sm8650.h81 .name = "sspp_2", .id = SSPP_VIG2,
H A Ddpu_8_0_sc8280xp.h91 .name = "sspp_2", .id = SSPP_VIG2,
H A Ddpu_9_2_x1e80100.h80 .name = "sspp_2", .id = SSPP_VIG2,