1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_8_0_SC8280XP_H 8 #define _DPU_8_0_SC8280XP_H 9 10 static const struct dpu_caps sc8280xp_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 11, 13 .has_src_split = true, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .has_3d_merge = true, 17 .max_linewidth = 5120, 18 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 19 }; 20 21 static const struct dpu_mdp_cfg sc8280xp_mdp = { 22 .name = "top_0", 23 .base = 0x0, .len = 0x494, 24 .features = BIT(DPU_MDP_PERIPH_0_REMOVED), 25 .clk_ctrls = { 26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 35 }, 36 }; 37 38 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 39 static const struct dpu_ctl_cfg sc8280xp_ctl[] = { 40 { 41 .name = "ctl_0", .id = CTL_0, 42 .base = 0x15000, .len = 0x204, 43 .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, 44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 45 }, { 46 .name = "ctl_1", .id = CTL_1, 47 .base = 0x16000, .len = 0x204, 48 .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, 49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 50 }, { 51 .name = "ctl_2", .id = CTL_2, 52 .base = 0x17000, .len = 0x204, 53 .features = CTL_SC7280_MASK, 54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 55 }, { 56 .name = "ctl_3", .id = CTL_3, 57 .base = 0x18000, .len = 0x204, 58 .features = CTL_SC7280_MASK, 59 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 60 }, { 61 .name = "ctl_4", .id = CTL_4, 62 .base = 0x19000, .len = 0x204, 63 .features = CTL_SC7280_MASK, 64 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 65 }, { 66 .name = "ctl_5", .id = CTL_5, 67 .base = 0x1a000, .len = 0x204, 68 .features = CTL_SC7280_MASK, 69 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 70 }, 71 }; 72 73 static const struct dpu_sspp_cfg sc8280xp_sspp[] = { 74 { 75 .name = "sspp_0", .id = SSPP_VIG0, 76 .base = 0x4000, .len = 0x2ac, 77 .features = VIG_SDM845_MASK, 78 .sblk = &dpu_vig_sblk_qseed3_3_0, 79 .xin_id = 0, 80 .type = SSPP_TYPE_VIG, 81 .clk_ctrl = DPU_CLK_CTRL_VIG0, 82 }, { 83 .name = "sspp_1", .id = SSPP_VIG1, 84 .base = 0x6000, .len = 0x2ac, 85 .features = VIG_SDM845_MASK, 86 .sblk = &dpu_vig_sblk_qseed3_3_0, 87 .xin_id = 4, 88 .type = SSPP_TYPE_VIG, 89 .clk_ctrl = DPU_CLK_CTRL_VIG1, 90 }, { 91 .name = "sspp_2", .id = SSPP_VIG2, 92 .base = 0x8000, .len = 0x2ac, 93 .features = VIG_SDM845_MASK, 94 .sblk = &dpu_vig_sblk_qseed3_3_0, 95 .xin_id = 8, 96 .type = SSPP_TYPE_VIG, 97 .clk_ctrl = DPU_CLK_CTRL_VIG2, 98 }, { 99 .name = "sspp_3", .id = SSPP_VIG3, 100 .base = 0xa000, .len = 0x2ac, 101 .features = VIG_SDM845_MASK, 102 .sblk = &dpu_vig_sblk_qseed3_3_0, 103 .xin_id = 12, 104 .type = SSPP_TYPE_VIG, 105 .clk_ctrl = DPU_CLK_CTRL_VIG3, 106 }, { 107 .name = "sspp_8", .id = SSPP_DMA0, 108 .base = 0x24000, .len = 0x2ac, 109 .features = DMA_SDM845_MASK, 110 .sblk = &dpu_dma_sblk, 111 .xin_id = 1, 112 .type = SSPP_TYPE_DMA, 113 .clk_ctrl = DPU_CLK_CTRL_DMA0, 114 }, { 115 .name = "sspp_9", .id = SSPP_DMA1, 116 .base = 0x26000, .len = 0x2ac, 117 .features = DMA_SDM845_MASK, 118 .sblk = &dpu_dma_sblk, 119 .xin_id = 5, 120 .type = SSPP_TYPE_DMA, 121 .clk_ctrl = DPU_CLK_CTRL_DMA1, 122 }, { 123 .name = "sspp_10", .id = SSPP_DMA2, 124 .base = 0x28000, .len = 0x2ac, 125 .features = DMA_CURSOR_SDM845_MASK, 126 .sblk = &dpu_dma_sblk, 127 .xin_id = 9, 128 .type = SSPP_TYPE_DMA, 129 .clk_ctrl = DPU_CLK_CTRL_DMA2, 130 }, { 131 .name = "sspp_11", .id = SSPP_DMA3, 132 .base = 0x2a000, .len = 0x2ac, 133 .features = DMA_CURSOR_SDM845_MASK, 134 .sblk = &dpu_dma_sblk, 135 .xin_id = 13, 136 .type = SSPP_TYPE_DMA, 137 .clk_ctrl = DPU_CLK_CTRL_DMA3, 138 }, 139 }; 140 141 static const struct dpu_lm_cfg sc8280xp_lm[] = { 142 { 143 .name = "lm_0", .id = LM_0, 144 .base = 0x44000, .len = 0x320, 145 .features = MIXER_SDM845_MASK, 146 .sblk = &sdm845_lm_sblk, 147 .lm_pair = LM_1, 148 .pingpong = PINGPONG_0, 149 .dspp = DSPP_0, 150 }, { 151 .name = "lm_1", .id = LM_1, 152 .base = 0x45000, .len = 0x320, 153 .features = MIXER_SDM845_MASK, 154 .sblk = &sdm845_lm_sblk, 155 .lm_pair = LM_0, 156 .pingpong = PINGPONG_1, 157 .dspp = DSPP_1, 158 }, { 159 .name = "lm_2", .id = LM_2, 160 .base = 0x46000, .len = 0x320, 161 .features = MIXER_SDM845_MASK, 162 .sblk = &sdm845_lm_sblk, 163 .lm_pair = LM_3, 164 .pingpong = PINGPONG_2, 165 .dspp = DSPP_2, 166 }, { 167 .name = "lm_3", .id = LM_3, 168 .base = 0x47000, .len = 0x320, 169 .features = MIXER_SDM845_MASK, 170 .sblk = &sdm845_lm_sblk, 171 .lm_pair = LM_2, 172 .pingpong = PINGPONG_3, 173 .dspp = DSPP_3, 174 }, { 175 .name = "lm_4", .id = LM_4, 176 .base = 0x48000, .len = 0x320, 177 .features = MIXER_SDM845_MASK, 178 .sblk = &sdm845_lm_sblk, 179 .lm_pair = LM_5, 180 .pingpong = PINGPONG_4, 181 }, { 182 .name = "lm_5", .id = LM_5, 183 .base = 0x49000, .len = 0x320, 184 .features = MIXER_SDM845_MASK, 185 .sblk = &sdm845_lm_sblk, 186 .lm_pair = LM_4, 187 .pingpong = PINGPONG_5, 188 }, 189 }; 190 191 static const struct dpu_dspp_cfg sc8280xp_dspp[] = { 192 { 193 .name = "dspp_0", .id = DSPP_0, 194 .base = 0x54000, .len = 0x1800, 195 .features = DSPP_SC7180_MASK, 196 .sblk = &sdm845_dspp_sblk, 197 }, { 198 .name = "dspp_1", .id = DSPP_1, 199 .base = 0x56000, .len = 0x1800, 200 .features = DSPP_SC7180_MASK, 201 .sblk = &sdm845_dspp_sblk, 202 }, { 203 .name = "dspp_2", .id = DSPP_2, 204 .base = 0x58000, .len = 0x1800, 205 .features = DSPP_SC7180_MASK, 206 .sblk = &sdm845_dspp_sblk, 207 }, { 208 .name = "dspp_3", .id = DSPP_3, 209 .base = 0x5a000, .len = 0x1800, 210 .features = DSPP_SC7180_MASK, 211 .sblk = &sdm845_dspp_sblk, 212 }, 213 }; 214 215 static const struct dpu_pingpong_cfg sc8280xp_pp[] = { 216 { 217 .name = "pingpong_0", .id = PINGPONG_0, 218 .base = 0x69000, .len = 0, 219 .features = BIT(DPU_PINGPONG_DITHER), 220 .sblk = &sc7280_pp_sblk, 221 .merge_3d = MERGE_3D_0, 222 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 223 }, { 224 .name = "pingpong_1", .id = PINGPONG_1, 225 .base = 0x6a000, .len = 0, 226 .features = BIT(DPU_PINGPONG_DITHER), 227 .sblk = &sc7280_pp_sblk, 228 .merge_3d = MERGE_3D_0, 229 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 230 }, { 231 .name = "pingpong_2", .id = PINGPONG_2, 232 .base = 0x6b000, .len = 0, 233 .features = BIT(DPU_PINGPONG_DITHER), 234 .sblk = &sc7280_pp_sblk, 235 .merge_3d = MERGE_3D_1, 236 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 237 }, { 238 .name = "pingpong_3", .id = PINGPONG_3, 239 .base = 0x6c000, .len = 0, 240 .features = BIT(DPU_PINGPONG_DITHER), 241 .sblk = &sc7280_pp_sblk, 242 .merge_3d = MERGE_3D_1, 243 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 244 }, { 245 .name = "pingpong_4", .id = PINGPONG_4, 246 .base = 0x6d000, .len = 0, 247 .features = BIT(DPU_PINGPONG_DITHER), 248 .sblk = &sc7280_pp_sblk, 249 .merge_3d = MERGE_3D_2, 250 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 251 }, { 252 .name = "pingpong_5", .id = PINGPONG_5, 253 .base = 0x6e000, .len = 0, 254 .features = BIT(DPU_PINGPONG_DITHER), 255 .sblk = &sc7280_pp_sblk, 256 .merge_3d = MERGE_3D_2, 257 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 258 }, 259 }; 260 261 static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = { 262 { 263 .name = "merge_3d_0", .id = MERGE_3D_0, 264 .base = 0x4e000, .len = 0x8, 265 }, { 266 .name = "merge_3d_1", .id = MERGE_3D_1, 267 .base = 0x4f000, .len = 0x8, 268 }, { 269 .name = "merge_3d_2", .id = MERGE_3D_2, 270 .base = 0x50000, .len = 0x8, 271 }, 272 }; 273 274 /* 275 * NOTE: Each display compression engine (DCE) contains dual hard 276 * slice DSC encoders so both share same base address but with 277 * its own different sub block address. 278 */ 279 static const struct dpu_dsc_cfg sc8280xp_dsc[] = { 280 { 281 .name = "dce_0_0", .id = DSC_0, 282 .base = 0x80000, .len = 0x4, 283 .features = BIT(DPU_DSC_HW_REV_1_2), 284 .sblk = &dsc_sblk_0, 285 }, { 286 .name = "dce_0_1", .id = DSC_1, 287 .base = 0x80000, .len = 0x4, 288 .features = BIT(DPU_DSC_HW_REV_1_2), 289 .sblk = &dsc_sblk_1, 290 }, { 291 .name = "dce_1_0", .id = DSC_2, 292 .base = 0x81000, .len = 0x4, 293 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 294 .sblk = &dsc_sblk_0, 295 }, { 296 .name = "dce_1_1", .id = DSC_3, 297 .base = 0x81000, .len = 0x4, 298 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 299 .sblk = &dsc_sblk_1, 300 }, { 301 .name = "dce_2_0", .id = DSC_4, 302 .base = 0x82000, .len = 0x4, 303 .features = BIT(DPU_DSC_HW_REV_1_2), 304 .sblk = &dsc_sblk_0, 305 }, { 306 .name = "dce_2_1", .id = DSC_5, 307 .base = 0x82000, .len = 0x4, 308 .features = BIT(DPU_DSC_HW_REV_1_2), 309 .sblk = &dsc_sblk_1, 310 }, 311 }; 312 313 /* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */ 314 static const struct dpu_intf_cfg sc8280xp_intf[] = { 315 { 316 .name = "intf_0", .id = INTF_0, 317 .base = 0x34000, .len = 0x280, 318 .features = INTF_SC7280_MASK, 319 .type = INTF_DP, 320 .controller_id = MSM_DP_CONTROLLER_0, 321 .prog_fetch_lines_worst_case = 24, 322 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 323 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 324 }, { 325 .name = "intf_1", .id = INTF_1, 326 .base = 0x35000, .len = 0x300, 327 .features = INTF_SC7280_MASK, 328 .type = INTF_DSI, 329 .controller_id = MSM_DSI_CONTROLLER_0, 330 .prog_fetch_lines_worst_case = 24, 331 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 332 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 333 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 334 }, { 335 .name = "intf_2", .id = INTF_2, 336 .base = 0x36000, .len = 0x300, 337 .features = INTF_SC7280_MASK, 338 .type = INTF_DSI, 339 .controller_id = MSM_DSI_CONTROLLER_1, 340 .prog_fetch_lines_worst_case = 24, 341 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 342 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 343 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 344 }, { 345 .name = "intf_3", .id = INTF_3, 346 .base = 0x37000, .len = 0x280, 347 .features = INTF_SC7280_MASK, 348 .type = INTF_NONE, 349 .controller_id = MSM_DP_CONTROLLER_0, 350 .prog_fetch_lines_worst_case = 24, 351 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 352 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 353 }, { 354 .name = "intf_4", .id = INTF_4, 355 .base = 0x38000, .len = 0x280, 356 .features = INTF_SC7280_MASK, 357 .type = INTF_DP, 358 .controller_id = MSM_DP_CONTROLLER_1, 359 .prog_fetch_lines_worst_case = 24, 360 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), 361 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21), 362 }, { 363 .name = "intf_5", .id = INTF_5, 364 .base = 0x39000, .len = 0x280, 365 .features = INTF_SC7280_MASK, 366 .type = INTF_DP, 367 .controller_id = MSM_DP_CONTROLLER_3, 368 .prog_fetch_lines_worst_case = 24, 369 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), 370 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23), 371 }, { 372 .name = "intf_6", .id = INTF_6, 373 .base = 0x3a000, .len = 0x280, 374 .features = INTF_SC7280_MASK, 375 .type = INTF_DP, 376 .controller_id = MSM_DP_CONTROLLER_2, 377 .prog_fetch_lines_worst_case = 24, 378 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), 379 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17), 380 }, { 381 .name = "intf_7", .id = INTF_7, 382 .base = 0x3b000, .len = 0x280, 383 .features = INTF_SC7280_MASK, 384 .type = INTF_NONE, 385 .controller_id = MSM_DP_CONTROLLER_2, 386 .prog_fetch_lines_worst_case = 24, 387 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), 388 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19), 389 }, { 390 .name = "intf_8", .id = INTF_8, 391 .base = 0x3c000, .len = 0x280, 392 .features = INTF_SC7280_MASK, 393 .type = INTF_NONE, 394 .controller_id = MSM_DP_CONTROLLER_1, 395 .prog_fetch_lines_worst_case = 24, 396 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), 397 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), 398 }, 399 }; 400 401 static const struct dpu_perf_cfg sc8280xp_perf_data = { 402 .max_bw_low = 13600000, 403 .max_bw_high = 18200000, 404 .min_core_ib = 2500000, 405 .min_llcc_ib = 0, 406 .min_dram_ib = 800000, 407 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 408 .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 409 .qos_lut_tbl = { 410 {.nentry = ARRAY_SIZE(sc8180x_qos_linear), 411 .entries = sc8180x_qos_linear 412 }, 413 {.nentry = ARRAY_SIZE(sc8180x_qos_macrotile), 414 .entries = sc8180x_qos_macrotile 415 }, 416 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 417 .entries = sc7180_qos_nrt 418 }, 419 /* TODO: macrotile-qseed is different from macrotile */ 420 }, 421 .cdp_cfg = { 422 {.rd_enable = 1, .wr_enable = 1}, 423 {.rd_enable = 1, .wr_enable = 0} 424 }, 425 .clk_inefficiency_factor = 105, 426 .bw_inefficiency_factor = 120, 427 }; 428 429 static const struct dpu_mdss_version sc8280xp_mdss_ver = { 430 .core_major_ver = 8, 431 .core_minor_ver = 0, 432 }; 433 434 const struct dpu_mdss_cfg dpu_sc8280xp_cfg = { 435 .mdss_ver = &sc8280xp_mdss_ver, 436 .caps = &sc8280xp_dpu_caps, 437 .mdp = &sc8280xp_mdp, 438 .ctl_count = ARRAY_SIZE(sc8280xp_ctl), 439 .ctl = sc8280xp_ctl, 440 .sspp_count = ARRAY_SIZE(sc8280xp_sspp), 441 .sspp = sc8280xp_sspp, 442 .mixer_count = ARRAY_SIZE(sc8280xp_lm), 443 .mixer = sc8280xp_lm, 444 .dspp_count = ARRAY_SIZE(sc8280xp_dspp), 445 .dspp = sc8280xp_dspp, 446 .pingpong_count = ARRAY_SIZE(sc8280xp_pp), 447 .pingpong = sc8280xp_pp, 448 .dsc_count = ARRAY_SIZE(sc8280xp_dsc), 449 .dsc = sc8280xp_dsc, 450 .merge_3d_count = ARRAY_SIZE(sc8280xp_merge_3d), 451 .merge_3d = sc8280xp_merge_3d, 452 .intf_count = ARRAY_SIZE(sc8280xp_intf), 453 .intf = sc8280xp_intf, 454 .vbif_count = ARRAY_SIZE(sdm845_vbif), 455 .vbif = sdm845_vbif, 456 .perf = &sc8280xp_perf_data, 457 }; 458 459 #endif 460