Searched refs:UVD_MPC_SET_MUXA0__VARA_3__SHIFT (Results 1 – 21 of 21) sorted by relevance
601 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT … macro
484 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
488 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
501 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x00000012 macro
520 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
522 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
1108 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT … macro
2849 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT … macro
2614 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT … macro
2841 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT … macro
3922 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT … macro
4039 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT … macro
4172 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT … macro
4215 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT … macro
925 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | in vcn_v4_0_5_start_dpg_mode()1064 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | in vcn_v4_0_5_start()
824 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | in vcn_v4_0_3_start_dpg_mode()1150 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | in vcn_v4_0_3_start()
874 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | in vcn_v1_0_start_spg_mode()1057 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | in vcn_v1_0_start_dpg_mode()
890 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | in vcn_v2_0_start_dpg_mode()1023 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | in vcn_v2_0_start()
1010 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | in vcn_v4_0_start_dpg_mode()1152 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | in vcn_v4_0_start()
919 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | in vcn_v2_5_start_dpg_mode()1073 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | in vcn_v2_5_start()
1039 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | in vcn_v3_0_start_dpg_mode()1203 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | in vcn_v3_0_start()