Home
last modified time | relevance | path

Searched refs:pic_width (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
H A Ddcn20_dsc.c179 if (dsc_cfg->pic_width > dsc20->max_image_width) in dsc2_validate_stream()
308 DC_LOG_DSC("\tpic_width %d", pps->pic_width); in dsc_log_pps()
384 ASSERT(dsc_cfg->pic_width); in dsc_prepare_config()
395 !dsc_cfg->pic_width || !dsc_cfg->pic_height || in dsc_prepare_config()
413 dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width; in dsc_prepare_config()
423 dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h; in dsc_prepare_config()
548 reg_vals->pps.pic_width = 0; in dsc_init_reg_values()
606 PIC_WIDTH, reg_vals->pps.pic_width, in dsc_write_to_registers()
655 PIC_WIDTH, reg_vals->pps.pic_width, in dsc_write_to_registers()
/linux/drivers/media/platform/chips-media/wave5/
H A Dwave5-hw.c596 info->pic_width = ((reg_val >> 16) & 0xffff); in wave5_get_dec_seq_result()
720 frame_width = init_info->pic_width; in wave5_vpu_dec_register_framebuffer()
1572 | p_open_param->pic_width); in wave5_vpu_enc_init_seq()
1776 buf_width = ALIGN(p_open_param->pic_width, 16); in wave5_vpu_enc_register_framebuffer()
1782 buf_width = ALIGN(p_open_param->pic_width, 16); in wave5_vpu_enc_register_framebuffer()
1791 buf_width = ALIGN(p_open_param->pic_width, 8); in wave5_vpu_enc_register_framebuffer()
1797 buf_width = ALIGN(p_open_param->pic_width, 32); in wave5_vpu_enc_register_framebuffer()
2354 u32 pic_width; in wave5_vpu_enc_check_open_param() local
2364 pic_width = open_param->pic_width; in wave5_vpu_enc_check_open_param()
2402 if (pic_width < W5_MIN_ENC_PIC_WIDTH || pic_width > W5_MAX_ENC_PIC_WIDTH || in wave5_vpu_enc_check_open_param()
[all …]
H A Dwave5-vpuapi.h367 u32 pic_width; member
574 u32 pic_width; /* width of a picture to be encoded in unit of sample */ member
H A Dwave5-vpu-dec.c376 __func__, initial_info->pic_width, initial_info->pic_height, in handle_dynamic_resolution_change()
393 inst->conf_win.width = initial_info->pic_width - in handle_dynamic_resolution_change()
398 wave5_update_pix_fmt(&inst->src_fmt, initial_info->pic_width, in handle_dynamic_resolution_change()
400 wave5_update_pix_fmt(&inst->dst_fmt, initial_info->pic_width, in handle_dynamic_resolution_change()
H A Dwave5-vpuapi.c300 if (stride < p_dec_info->initial_info.pic_width || (stride % 8 != 0) || in wave5_vpu_dec_register_frame_buffer_ex()
H A Dwave5-vpu-enc.c1150 open_param->pic_width = inst->dst_fmt.width; in wave5_set_enc_openparam()
/linux/include/drm/display/
H A Ddrm_dsc.h107 u16 pic_width; member
345 __be16 pic_width; member
/linux/drivers/gpu/drm/amd/display/dc/dsc/
H A Ddc_dsc.c874 int pic_width; in setup_dsc_config() local
887 pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right; in setup_dsc_config()
893 if (dsc_sink_caps->branch_max_line_width && dsc_sink_caps->branch_max_line_width < pic_width) in setup_dsc_config()
966 if (pic_width % max_slices_h == 0) in setup_dsc_config()
976 min_slices_h = pic_width / dsc_common_caps.max_slice_width; in setup_dsc_config()
977 if (pic_width % dsc_common_caps.max_slice_width) in setup_dsc_config()
992 if (pic_width % min_slices_h != 0) in setup_dsc_config()
1034 slice_width = pic_width / num_slices_h; in setup_dsc_config()
H A Drc_calc_dpi.c39 to->pic_width = from->pic_width; in copy_pps_fields()
H A Ddsc.h38 uint32_t pic_width; member
/linux/drivers/gpu/drm/i915/display/
H A Dintel_vdsc.c271 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; in intel_dsc_compute_params()
272 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, in intel_dsc_compute_params()
470 DSC_PPS2_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); in intel_dsc_pps_configure()
528 DSC_PPS16_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / in intel_dsc_pps_configure()
890 vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PPS2_PIC_WIDTH_MASK, pps_temp) * num_vdsc_instances; in intel_dsc_get_pps_config()
H A Dintel_vdsc_regs.h99 #define DSC_PPS2_PIC_WIDTH(pic_width) REG_FIELD_PREP(DSC_PPS2_PIC_WIDTH_MASK, pic_width) argument
H A Dicl_dsi.c1600 vdsc_cfg->pic_width % vdsc_cfg->slice_width); in gen11_dsi_dsc_compute_config()
H A Dintel_display.c5378 PIPE_CONF_CHECK_I(dsc.config.pic_width); in intel_pipe_config_compare()
/linux/drivers/gpu/drm/display/
H A Ddrm_dsc_helper.c144 pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width); in drm_dsc_pps_payload_pack()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
H A Ddcn314_hwseq.c89 …dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.… in update_dsc_on_stream()
108 dsc_cfg.pic_width *= opp_cnt; in update_dsc_on_stream()
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_dsc.c75 data = dsc->pic_width << 16; in dpu_hw_dsc_config()
H A Ddpu_hw_dsc_1_2.c157 data = (dsc->pic_width & 0xffff) | in dpu_hw_dsc_config_1_2()
H A Ddpu_encoder.c1910 int pic_width; in dpu_encoder_prep_dsc() local
1925 pic_width = dsc->pic_width; in dpu_encoder_prep_dsc()
1933 this_frame_slices = pic_width / dsc->slice_width; in dpu_encoder_prep_dsc()
/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi_host.c952 dsc->pic_width = mode->hdisplay; in dsi_timing_setup()
954 DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); in dsi_timing_setup()
2503 int pic_width = mode->hdisplay; in msm_dsi_host_check_dsc() local
2509 if (pic_width % dsc->slice_width) { in msm_dsi_host_check_dsc()
2511 pic_width, dsc->slice_width); in msm_dsi_host_check_dsc()
/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.c811 …dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.… in link_set_dsc_on_stream()
833 dsc_cfg.pic_width *= opp_cnt; in link_set_dsc_on_stream()
921 …dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h… in link_set_dsc_pps_packet()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c380 …dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.… in update_dsc_on_stream()
399 dsc_cfg.pic_width *= opp_cnt; in update_dsc_on_stream()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c996 …dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.… in update_dsc_on_stream()
1019 dsc_cfg.pic_width *= opp_cnt; in update_dsc_on_stream()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1684 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left in dcn20_validate_dsc()