| /linux/drivers/gpu/drm/tegra/ |
| H A D | mipi-phy.c | 28 timing->eot = 0; in mipi_dphy_timing_get_default()
50 timing->taget = 5 * timing->lpx; in mipi_dphy_timing_get_default()
51 timing->tago = 4 * timing->lpx; in mipi_dphy_timing_get_default()
52 timing->tasure = 2 * timing->lpx; in mipi_dphy_timing_get_default()
74 if (timing->clkprepare < 38 || timing->clkprepare > 95) in mipi_dphy_timing_validate()
77 if (timing->clksettle < 95 || timing->clksettle > 300) in mipi_dphy_timing_validate()
86 if (timing->clkprepare + timing->clkzero < 300) in mipi_dphy_timing_validate()
102 if (timing->hsprepare + timing->hszero < 145 + 10 * period) in mipi_dphy_timing_validate()
121 if (timing->taget != 5 * timing->lpx) in mipi_dphy_timing_validate()
124 if (timing->tago != 4 * timing->lpx) in mipi_dphy_timing_validate()
[all …]
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| /linux/drivers/gpu/drm/msm/dsi/phy/ |
| H A D | dsi_phy.c | 138 timing->clk_trail, timing->clk_prepare, timing->hs_exit, in msm_dsi_dphy_timing_calc()
139 timing->hs_zero, timing->hs_prepare, timing->hs_trail, in msm_dsi_dphy_timing_calc()
252 timing->clk_trail, timing->clk_prepare, timing->hs_exit, in msm_dsi_dphy_timing_calc_v2()
253 timing->hs_zero, timing->hs_prepare, timing->hs_trail, in msm_dsi_dphy_timing_calc_v2()
254 timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en, in msm_dsi_dphy_timing_calc_v2()
362 timing->clk_trail, timing->clk_prepare, timing->hs_exit, in msm_dsi_dphy_timing_calc_v3()
363 timing->hs_zero, timing->hs_prepare, timing->hs_trail, in msm_dsi_dphy_timing_calc_v3()
364 timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en, in msm_dsi_dphy_timing_calc_v3()
463 timing->clk_zero, timing->clk_trail, timing->clk_prepare, timing->hs_exit, in msm_dsi_dphy_timing_calc_v4()
464 timing->hs_zero, timing->hs_prepare, timing->hs_trail, timing->hs_rqst); in msm_dsi_dphy_timing_calc_v4()
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| H A D | dsi_phy_20nm.c | 11 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
16 DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_20nm_dphy_set_timing()
21 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
25 DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_20nm_dphy_set_timing()
27 DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_20nm_dphy_set_timing()
33 DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); in dsi_20nm_dphy_set_timing()
35 DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) | in dsi_20nm_dphy_set_timing()
38 DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get)); in dsi_20nm_dphy_set_timing()
70 struct msm_dsi_dphy_timing *timing = &phy->timing; in dsi_20nm_phy_enable() local
78 if (msm_dsi_dphy_timing_calc(timing, clk_req)) { in dsi_20nm_phy_enable()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_validation.c | 41 uint32_t pxl_clk = timing->pix_clk_100hz; in get_tmds_output_pixel_clock_100hz()
57 const struct dc_crtc_timing *timing, in dp_active_dongle_validate_timing() argument
77 switch (timing->pixel_encoding) { in dp_active_dongle_validate_timing()
94 switch (timing->display_color_depth) { in dp_active_dongle_validate_timing()
115 switch (timing->timing_3d_format) { in dp_active_dongle_validate_timing()
128 if (timing->flags.DSC && !timing->dsc_cfg.is_frl) in dp_active_dongle_validate_timing()
260 const struct dc_crtc_timing *timing) in dp_validate_mode_timing() argument
275 timing->h_addressable == (uint32_t) 640 && in dp_validate_mode_timing()
276 timing->v_addressable == (uint32_t) 480) in dp_validate_mode_timing()
312 const struct dc_crtc_timing *timing) in link_validate_mode_timing() argument
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| /linux/drivers/clk/tegra/ |
| H A D | clk-tegra124-emc.c | 154 if (timing) { in emc_determine_rate()
222 timing->parent_rate, __clk_get_name(timing->parent)); in emc_set_timing()
225 clk_get_rate(timing->parent) != timing->parent_rate) { in emc_set_timing()
235 err = clk_set_rate(timing->parent, timing->parent_rate); in emc_set_timing()
238 __clk_get_name(timing->parent), timing->parent_rate, in emc_set_timing()
250 div = timing->parent_rate / (timing->rate / 2) - 2; in emc_set_timing()
304 return timing; in get_backup_timing()
315 return timing; in get_backup_timing()
350 if (!timing) { in emc_set_rate()
357 clk_get_rate(timing->parent) != timing->parent_rate) { in emc_set_rate()
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| H A D | timing.c | 33 u32 timing = 0; in nvbios_timingTe() local
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
51 return timing; in nvbios_timingTe()
53 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
58 return timing; in nvbios_timingTe()
74 if (timing && idx < *cnt) { in nvbios_timingEe()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/ |
| H A D | dcn201_optc.c | 44 return optc1_is_two_pixels_per_containter(timing); in optc201_is_two_pixels_per_containter()
76 const struct dc_crtc_timing *timing) in optc201_validate_timing() argument
83 ASSERT(timing != NULL); in optc201_validate_timing()
85 v_blank = (timing->v_total - timing->v_addressable - in optc201_validate_timing()
86 timing->v_border_top - timing->v_border_bottom); in optc201_validate_timing()
88 h_blank = (timing->h_total - timing->h_addressable - in optc201_validate_timing()
89 timing->h_border_right - in optc201_validate_timing()
90 timing->h_border_left); in optc201_validate_timing()
105 if (timing->h_total > optc1->max_h_total || in optc201_validate_timing()
106 timing->v_total > optc1->max_v_total) in optc201_validate_timing()
[all …]
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| /linux/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_encoder_phys_vid.c | 47 memset(timing, 0, sizeof(*timing)); in drm_mode_to_intf_timing_params()
76 timing->xres = timing->width; in drm_mode_to_intf_timing_params()
77 timing->yres = timing->height; in drm_mode_to_intf_timing_params()
98 timing->h_back_porch += timing->h_front_porch; in drm_mode_to_intf_timing_params()
100 timing->v_back_porch += timing->v_front_porch; in drm_mode_to_intf_timing_params()
112 timing->width = timing->width >> 1; in drm_mode_to_intf_timing_params()
113 timing->xres = timing->xres >> 1; in drm_mode_to_intf_timing_params()
114 timing->h_back_porch = timing->h_back_porch >> 1; in drm_mode_to_intf_timing_params()
124 timing->h_back_porch + timing->h_front_porch + in get_horizontal_total()
133 timing->v_back_porch + timing->v_front_porch + in get_vertical_total()
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| /linux/drivers/video/fbdev/ |
| H A D | gbefb.c | 503 if (timing) { in compute_gbe_timing()
510 (timing->pll_n << timing->pll_p); in compute_gbe_timing()
515 timing->fields_sec = 1000 * timing->cfreq / timing->htotal * in compute_gbe_timing()
519 timing->hblank_end = timing->htotal; in compute_gbe_timing()
522 timing->vblank_end = timing->vtotal; in compute_gbe_timing()
581 temp = timing->vblank_start - timing->vblank_end - 1; in gbe_set_timing_info()
594 timing->htotal - (20 - timing->hblank_end)); in gbe_set_timing_info()
984 var->left_margin = timing.htotal - timing.hsync_end; in gbefb_check_var()
985 var->right_margin = timing.hsync_start - timing.width; in gbefb_check_var()
986 var->upper_margin = timing.vtotal - timing.vsync_end; in gbefb_check_var()
[all …]
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| /linux/drivers/video/fbdev/via/ |
| H A D | via_modesetting.c | 22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
27 raw.hor_sync_end = timing->hor_sync_end / 8; in via_set_primary_timing()
28 raw.ver_total = timing->ver_total - 2; in via_set_primary_timing()
29 raw.ver_addr = timing->ver_addr - 1; in via_set_primary_timing()
31 raw.ver_blank_end = timing->ver_blank_end - 1; in via_set_primary_timing()
33 raw.ver_sync_end = timing->ver_sync_end - 1; in via_set_primary_timing()
80 raw.hor_total = timing->hor_total - 1; in via_set_secondary_timing()
81 raw.hor_addr = timing->hor_addr - 1; in via_set_secondary_timing()
86 raw.ver_total = timing->ver_total - 1; in via_set_secondary_timing()
[all …]
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| /linux/drivers/gpu/drm/sti/ |
| H A D | sti_awg_utils.c | 122 struct awg_timing *timing) in awg_generate_line_signal() argument
127 if (timing->trailing_pixels > 0) { in awg_generate_line_signal()
129 val = timing->blanking_level; in awg_generate_line_signal()
137 val = timing->blanking_level; in awg_generate_line_signal()
143 val = timing->active_pixels - 1; in awg_generate_line_signal()
147 val = timing->blanking_level; in awg_generate_line_signal()
156 struct awg_timing *timing) in sti_awg_generate_code_data_enable_mode() argument
161 if (timing->trailing_lines > 0) { in sti_awg_generate_code_data_enable_mode()
163 val = timing->blanking_level; in sti_awg_generate_code_data_enable_mode()
182 if (timing->blanking_lines > 0) { in sti_awg_generate_code_data_enable_mode()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/ |
| H A D | dc_dsc.c | 63 if (!timing->flags.DSC) { in apply_128b_132b_stream_overhead()
94 if (timing->flags.DSC) in dc_bandwidth_in_kbps_from_timing()
96 timing->dsc_cfg.bits_per_pixel, in dc_bandwidth_in_kbps_from_timing()
97 timing->dsc_cfg.num_slices_h, in dc_bandwidth_in_kbps_from_timing()
98 timing->dsc_cfg.is_dp); in dc_bandwidth_in_kbps_from_timing()
128 if (timing->flags.Y_ONLY != 1) { in dc_bandwidth_in_kbps_from_timing()
141 timing->vic == 0 && timing->hdmi_vic == 0 && in dc_bandwidth_in_kbps_from_timing()
887 pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right; in setup_dsc_config()
888 pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom; in setup_dsc_config()
1070 timing, in setup_dsc_config()
[all …]
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| H A D | ramnv50.c | 143 timing[0], timing[1], timing[2], timing[3]); in nv50_ram_timing_calc()
145 timing[4], timing[5], timing[6], timing[7]); in nv50_ram_timing_calc()
389 ram_mask(hwsq, timing[3], 0xffffffff, timing[3]); in nv50_ram_calc()
390 ram_mask(hwsq, timing[1], 0xffffffff, timing[1]); in nv50_ram_calc()
391 ram_mask(hwsq, timing[6], 0xffffffff, timing[6]); in nv50_ram_calc()
392 ram_mask(hwsq, timing[7], 0xffffffff, timing[7]); in nv50_ram_calc()
393 ram_mask(hwsq, timing[8], 0xffffffff, timing[8]); in nv50_ram_calc()
394 ram_mask(hwsq, timing[0], 0xffffffff, timing[0]); in nv50_ram_calc()
395 ram_mask(hwsq, timing[2], 0xffffffff, timing[2]); in nv50_ram_calc()
396 ram_mask(hwsq, timing[4], 0xffffffff, timing[4]); in nv50_ram_calc()
[all …]
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| /linux/drivers/memory/tegra/ |
| H A D | tegra124-emc.c | 587 if (!timing) { in tegra_emc_find_timing()
592 return timing; in tegra_emc_find_timing()
606 if (!timing) in tegra_emc_prepare_timing_change()
746 val = timing->emc_cfg_2; in tegra_emc_prepare_timing_change()
830 if (!timing) in tegra_emc_complete_timing_change()
875 emc->last_timing = *timing; in tegra_emc_complete_timing_change()
893 timing->emc_mode_1 = 0; in emc_read_current_timing()
894 timing->emc_mode_2 = 0; in emc_read_current_timing()
895 timing->emc_mode_4 = 0; in emc_read_current_timing()
934 timing->rate = value; in load_one_timing_from_dt()
[all …]
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| H A D | tegra30-emc.c | 445 timing = &emc->timings[i]; in emc_find_timing()
450 if (!timing) { in emc_find_timing()
455 return timing; in emc_find_timing()
617 val ^= timing->data[74]; in emc_prepare_timing_change()
902 timing->rate = value; in load_one_timing_from_dt()
905 timing->data, in load_one_timing_from_dt()
983 struct emc_timing *timing; in emc_load_timings_from_dt() local
999 timing = emc->timings; in emc_load_timings_from_dt()
1221 timing = &emc->timings[i]; in emc_round_rate()
1225 if (!timing) { in emc_round_rate()
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| /linux/drivers/media/i2c/ |
| H A D | bt819.c | 60 struct timing { struct
70 static struct timing timing_data[] = { argument
175 struct timing *timing = &timing_data[(decoder->norm & V4L2_STD_525_60) ? 1 : 0]; in bt819_init() local
181 ((timing->hactive >> 8) & 0x03); in bt819_init()
186 init[0x08 * 2 - 1] = timing->hscale >> 8; in bt819_init()
238 struct timing *timing = NULL; in bt819_s_std() local
253 timing = &timing_data[1]; in bt819_s_std()
262 timing = &timing_data[0]; in bt819_s_std()
269 (((timing->vdelay >> 8) & 0x03) << 6) | in bt819_s_std()
271 (((timing->hdelay >> 8) & 0x03) << 2) | in bt819_s_std()
[all …]
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| /linux/drivers/leds/ |
| H A D | leds-expresswire.c | 19 usleep_range(props->timing.poweroff_us, props->timing.poweroff_us * 2); in expresswire_power_off()
26 udelay(props->timing.detect_delay_us); in expresswire_enable()
28 udelay(props->timing.detect_us); in expresswire_enable()
36 udelay(props->timing.data_start_us); in expresswire_start()
43 udelay(props->timing.end_of_data_low_us); in expresswire_end()
45 udelay(props->timing.end_of_data_high_us); in expresswire_end()
53 udelay(props->timing.short_bitset_us); in expresswire_set_bit()
55 udelay(props->timing.long_bitset_us); in expresswire_set_bit()
58 udelay(props->timing.long_bitset_us); in expresswire_set_bit()
60 udelay(props->timing.short_bitset_us); in expresswire_set_bit()
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| /linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| H A D | dce110_timing_generator_v.c | 246 timing->v_front_porch; in dce110_timing_generator_v_program_blanking()
250 timing->h_front_porch; in dce110_timing_generator_v_program_blanking()
262 timing->h_total - 1, in dce110_timing_generator_v_program_blanking()
271 timing->v_total - 1, in dce110_timing_generator_v_program_blanking()
279 tmp = timing->h_total - in dce110_timing_generator_v_program_blanking()
289 timing->h_border_left + timing->h_border_right; in dce110_timing_generator_v_program_blanking()
302 tmp = timing->v_total - (v_sync_start + timing->v_border_top); in dce110_timing_generator_v_program_blanking()
310 tmp = tmp + timing->v_addressable + timing->v_border_top + in dce110_timing_generator_v_program_blanking()
325 timing->h_sync_width, in dce110_timing_generator_v_program_blanking()
351 timing->v_sync_width, in dce110_timing_generator_v_program_blanking()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_resource_helpers.c | 443 timing = &fpo_candidate_stream->timing; in get_frame_rate_at_max_stretch_100hz()
444 if (timing == NULL) in get_frame_rate_at_max_stretch_100hz()
449 sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1; in get_frame_rate_at_max_stretch_100hz()
451 curr_v_blank = timing->v_total - timing->v_addressable; in get_frame_rate_at_max_stretch_100hz()
453 stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total; in get_frame_rate_at_max_stretch_100hz()
489 timing = &fpo_candidate_stream->timing; in get_refresh_rate()
490 if (timing == NULL) in get_refresh_rate()
493 h_v_total = timing->h_total * timing->v_total; in get_refresh_rate()
617 if (pipe->stream->timing.v_addressable == 1080 && pipe->stream->timing.h_addressable == 1920) in disallow_subvp_in_active_plus_blank()
659 pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1); in dcn32_subvp_drr_admissable()
[all …]
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| H A D | dcn32_dio_stream_encoder.c | 237 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; in is_two_pixels_per_containter()
239 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 in is_two_pixels_per_containter()
240 && !timing->dsc_cfg.ycbcr422_simple); in is_two_pixels_per_containter()
254 if (timing) { in is_h_timing_divisible_by_2()
255 h_blank_start = timing->h_total - timing->h_front_porch; in is_h_timing_divisible_by_2()
256 h_blank_end = h_blank_start - timing->h_addressable; in is_h_timing_divisible_by_2()
262 divisible = (timing->h_total % 2 == 0) && in is_h_timing_divisible_by_2()
265 (timing->h_sync_width % 2 == 0); in is_h_timing_divisible_by_2()
273 return is_h_timing_divisible_by_2(timing) && in is_dp_dig_pixel_rate_div_policy()
294 || is_dp_dig_pixel_rate_div_policy(dc, ¶m->timing)) { in enc32_stream_encoder_dp_unblank()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml2_mall_phantom.c | 247 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) in assign_subvp_pipe()
248 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); in assign_subvp_pipe()
266 unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total / in assign_subvp_pipe()
377 microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) + in subvp_subvp_schedulable()
378 phantom->timing.v_addressable; in subvp_subvp_schedulable()
396 …vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_to… in subvp_subvp_schedulable()
398 …vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_to… in subvp_subvp_schedulable()
462 main_timing = &pipe->stream->timing; in dml2_svp_drr_schedulable()
691 line_time = phantom_stream->timing.h_total / ((double)phantom_stream->timing.pix_clk_100hz * 100); in set_phantom_stream_timing()
708 phantom_stream->timing.v_total = phantom_stream->timing.v_addressable + in set_phantom_stream_timing()
[all …]
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| /linux/drivers/ata/ |
| H A D | pata_triflex.c | 76 u32 timing = 0; in triflex_load_timing() local
88 timing = 0x0103;break; in triflex_load_timing()
90 timing = 0x0203;break; in triflex_load_timing()
92 timing = 0x0808;break; in triflex_load_timing()
96 timing = 0x0F0F;break; in triflex_load_timing()
98 timing = 0x0202;break; in triflex_load_timing()
100 timing = 0x0204;break; in triflex_load_timing()
102 timing = 0x0404;break; in triflex_load_timing()
104 timing = 0x0508;break; in triflex_load_timing()
106 timing = 0x0808;break; in triflex_load_timing()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dce120/ |
| H A D | dce120_timing_generator.c | 108 (timing->v_total - timing->v_addressable - in dce120_timing_generator_validate_timing()
109 timing->v_border_top - timing->v_border_bottom) * in dce120_timing_generator_validate_timing()
115 timing, in dce120_timing_generator_validate_timing()
446 timing->h_total - 1); in dce120_timing_generator_program_blanking()
451 timing->v_total - 1); in dce120_timing_generator_program_blanking()
459 timing->v_total - 1); in dce120_timing_generator_program_blanking()
469 timing->h_border_left + timing->h_border_right; in dce120_timing_generator_program_blanking()
476 tmp1 = timing->v_total - (v_sync_start + timing->v_border_top); in dce120_timing_generator_program_blanking()
477 tmp2 = tmp1 + timing->v_addressable + timing->v_border_top + in dce120_timing_generator_program_blanking()
628 timing->v_total - timing->v_addressable - in dce120_timing_generator_enable_advanced_request()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 288 (((float)timing->h_total * 1000.0) / in micro_sec_to_vert_lines()
289 ((float)timing->pix_clk_100hz / 10.0)); in micro_sec_to_vert_lines()
300 v_active = timing->v_border_top + timing->v_addressable + timing->v_border_bottom; in get_vertical_back_porch()
301 v_blank = timing->v_total - v_active; in get_vertical_back_porch()
302 v_back_porch = v_blank - timing->v_front_porch - timing->v_sync_width; in get_vertical_back_porch()
322 struct dc_crtc_timing *timing; in dcn314_populate_dml_pipes_from_context_fpu() local
329 timing = &pipe->stream->timing; in dcn314_populate_dml_pipes_from_context_fpu()
336 pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total; in dcn314_populate_dml_pipes_from_context_fpu()
338 v_back_porch = get_vertical_back_porch(timing); in dcn314_populate_dml_pipes_from_context_fpu()
369 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; in dcn314_populate_dml_pipes_from_context_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn35/ |
| H A D | dcn35_dio_stream_encoder.c | 269 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; in is_two_pixels_per_containter()
271 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 in is_two_pixels_per_containter()
272 && !timing->dsc_cfg.ycbcr422_simple); in is_two_pixels_per_containter()
286 if (timing) { in is_h_timing_divisible_by_2()
287 h_blank_start = timing->h_total - timing->h_front_porch; in is_h_timing_divisible_by_2()
288 h_blank_end = h_blank_start - timing->h_addressable; in is_h_timing_divisible_by_2()
294 divisible = (timing->h_total % 2 == 0) && in is_h_timing_divisible_by_2()
297 (timing->h_sync_width % 2 == 0); in is_h_timing_divisible_by_2()
305 return is_h_timing_divisible_by_2(timing) && in is_dp_dig_pixel_rate_div_policy()
326 || is_dp_dig_pixel_rate_div_policy(dc, ¶m->timing)) { in enc35_stream_encoder_dp_unblank()
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