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Searched refs:AR_PHY_TIMING_CTRL4_0 (Results 1 – 6 of 6) sorted by relevance

/netbsd/sys/dev/ic/
H A Darn9280.c256 reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset); in ar9280_init_from_rom()
261 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg); in ar9280_init_from_rom()
495 AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0, in ar9280_spur_mitigate()
H A Darn5416.c247 reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset); in ar5416_init_from_rom()
252 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg); in ar5416_init_from_rom()
698 AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0, in ar5416_spur_mitigate()
H A Darn9287.c175 reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset); in ar9287_init_from_rom()
180 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg); in ar9287_init_from_rom()
H A Darn9285.c194 reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0); in ar9285_init_from_rom()
197 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0, reg); in ar9285_init_from_rom()
H A Darn5008.c1990 reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0); in ar5008_do_calib()
1993 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0, reg); in ar5008_do_calib()
2004 AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0, AR_PHY_TIMING_CTRL4_DO_CAL); in ar5008_do_calib()
2014 if (!(AR_READ(sc, AR_PHY_TIMING_CTRL4_0) & in ar5008_next_calib()
2086 AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0, in ar5008_calib_iq()
H A Darn5008reg.h93 #define AR_PHY_TIMING_CTRL4_0 0x9920 macro