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Searched refs:CACHE_LINE_SIZE (Results 1 – 25 of 37) sorted by relevance

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/netbsd/sys/external/bsd/vchiq/dist/interface/vchiq_arm/
H A Dvchiq_pagelist.h40 #undef CACHE_LINE_SIZE
41 #define CACHE_LINE_SIZE 32 macro
55 char headbuf[CACHE_LINE_SIZE];
56 char tailbuf[CACHE_LINE_SIZE];
/netbsd/sys/external/bsd/drm2/linux/
H A Dlinux_atomic64.c59 char pad[CACHE_LINE_SIZE -
61 } atomic64_tab[PAGE_SIZE/CACHE_LINE_SIZE] __cacheline_aligned;
63 CTASSERT(sizeof(atomic64_tab[0]) == CACHE_LINE_SIZE);
93 return ((uintptr_t)a >> ilog2(CACHE_LINE_SIZE)) % in atomic64_hash()
H A Dlinux_wait_bit.c51 char pad[CACHE_LINE_SIZE - sizeof(struct waitbitentry)];
52 } waitbittab[PAGE_SIZE/CACHE_LINE_SIZE] __cacheline_aligned;
54 CTASSERT(sizeof(waitbittab[0]) == CACHE_LINE_SIZE);
86 return ((uintptr_t)word >> ilog2(CACHE_LINE_SIZE)) % in wait_bit_hash()
/netbsd/sys/sys/
H A Dfiledesc.h115 #define FDFILE_SIZE ((sizeof(fdfile_t)+CACHE_LINE_SIZE-1)/CACHE_LINE_SIZE*CACHE_LINE_SIZE)
H A Dpool.h281 __aligned(CACHE_LINE_SIZE);
285 pool_cache_cpu_t pc_cpu0 __aligned(CACHE_LINE_SIZE);
H A Dparam.h153 #ifndef CACHE_LINE_SIZE
154 #define CACHE_LINE_SIZE 64 macro
/netbsd/sys/dev/pci/
H A Dif_enavar.h210 } __aligned(CACHE_LINE_SIZE);
216 } __aligned(CACHE_LINE_SIZE);
326 } __aligned(CACHE_LINE_SIZE);
399 __aligned(CACHE_LINE_SIZE); /* stable */
403 __aligned(CACHE_LINE_SIZE);
407 __aligned(CACHE_LINE_SIZE);
/netbsd/sys/arch/riscv/riscv/
H A Dcpu.c65 u_int riscv_dcache_align = CACHE_LINE_SIZE;
66 u_int riscv_dcache_align_mask = CACHE_LINE_SIZE - 1;
H A Dpmap_machdep.c407 pmap_pvlist_lock_init(CACHE_LINE_SIZE); in pmap_bootstrap()
/netbsd/sys/arch/xen/x86/
H A Dcpu.c153 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = {
160 struct cpu_info phycpu_info_primary __aligned(CACHE_LINE_SIZE) = {
214 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, in cpu_attach()
216 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); in cpu_attach()
381 ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, in cpu_attach_common()
383 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); in cpu_attach_common()
/netbsd/sys/netinet/
H A Dtcp_vtw.h154 #if CACHE_LINE_SIZE == 128
165 #define FATP_NTAGS (CACHE_LINE_SIZE / sizeof(fatp_word_t) - 1)
H A Dtcp_vtw.c259 CTASSERT(CACHE_LINE_SIZE == 32 || in fatp_key()
260 CACHE_LINE_SIZE == 64 || in fatp_key()
261 CACHE_LINE_SIZE == 128); in fatp_key()
279 CTASSERT(CACHE_LINE_SIZE == 32 || in fatp_slot_from_key()
280 CACHE_LINE_SIZE == 64 || in fatp_slot_from_key()
281 CACHE_LINE_SIZE == 128); in fatp_slot_from_key()
299 CTASSERT(CACHE_LINE_SIZE == 32 || in fatp_from_key()
300 CACHE_LINE_SIZE == 64 || in fatp_from_key()
301 CACHE_LINE_SIZE == 128); in fatp_from_key()
/netbsd/sys/kern/
H A Dkern_lock.c64 __cpu_simple_lock_t kernel_lock[CACHE_LINE_SIZE / sizeof(__cpu_simple_lock_t)]
167 CTASSERT(CACHE_LINE_SIZE >= sizeof(__cpu_simple_lock_t));
H A Dsubr_ipi.c73 #define IPI_MSG_SLOTS (CACHE_LINE_SIZE / sizeof(ipi_msg_t *))
/netbsd/sys/arch/aarch64/include/
H A Dparam.h147 #define CACHE_LINE_SIZE 128 macro
/netbsd/sys/arch/mips/include/
H A Dmips_param.h103 #define CACHE_LINE_SIZE 128 macro
/netbsd/sys/arch/ia64/ia64/
H A Dcpu.c50 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE);
/netbsd/sys/arch/x86/x86/
H A Dcpu.c173 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = {
377 sizeof(*ci) + CACHE_LINE_SIZE - 1, 0, in cpu_attach()
379 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); in cpu_attach()
/netbsd/sys/external/bsd/common/include/linux/
H A Dslab.h206 align = roundup(MAX(1, align), CACHE_LINE_SIZE); in kmem_cache_create_dtor()
/netbsd/sys/arch/sparc/sparc/
H A Dtimer.c97 } cntr __aligned(CACHE_LINE_SIZE);
/netbsd/sys/dev/hyperv/
H A Dvmbusvar.h168 } __aligned(CACHE_LINE_SIZE);
/netbsd/sys/dev/usb/
H A Dehcivar.h46 #define EHCI_SQTD_ALIGN MAX(EHCI_QTD_ALIGN, CACHE_LINE_SIZE)
H A Dusb_mem.c66 #define USB_MEM_SMALL roundup(64, CACHE_LINE_SIZE)
/netbsd/sys/rump/librump/rumpkern/
H A Dscheduler.c68 int rcpu_align[0] __aligned(CACHE_LINE_SIZE);
/netbsd/sys/external/bsd/ena-com/
H A Dena_plat.h117 #define ____cacheline_aligned __aligned(CACHE_LINE_SIZE)

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