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Searched refs:CP_ME2_PIPE0_INT_CNTL (Results 1 – 4 of 4) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/radeon/
H A Dcikd.h1364 #define CP_ME2_PIPE0_INT_CNTL 0xC224 macro
H A Dradeon_cik.c6900 WREG32(CP_ME2_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
7083 cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7254 WREG32(CP_ME2_PIPE0_INT_CNTL, cp_m2p0); in cik_irq_set()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gfx_v10_0.c5094 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, in gfx_v10_0_kiq_set_interrupt_state()
5104 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, in gfx_v10_0_kiq_set_interrupt_state()
H A Damdgpu_gfx_v8_0.c6662 WREG32_FIELD(CP_ME2_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, in gfx_v8_0_set_cp_ecc_int_state()