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Searched refs:CP_MEC_CNTL__MEC_ME2_HALT_MASK (Results 1 – 11 of 11) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gfx_v7_0.c2716 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v7_0_cp_compute_enable()
4676 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); in gfx_v7_0_soft_reset()
H A Damdgpu_gfx_v10_0.c2886 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v10_0_cp_compute_enable()
H A Damdgpu_gfx_v9_0.c3254 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v9_0_cp_compute_enable()
H A Damdgpu_gfx_v8_0.c4327 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v8_0_cp_compute_enable()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h2223 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000 macro
H A Dgfx_8_1_sh_mask.h3291 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000 macro
H A Dgfx_8_0_sh_mask.h2769 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000 macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h848 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK … macro
H A Dgc_9_1_sh_mask.h747 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK … macro
H A Dgc_9_2_1_sh_mask.h736 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK … macro
H A Dgc_10_1_0_sh_mask.h6323 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK … macro