1 /* $NetBSD: cycv_reg.h,v 1.2 2018/10/18 09:01:52 skrll Exp $ */ 2 #ifndef _ARM_ALTERA_CYCV_REG_H 3 #define _ARM_ALTERA_CYCV_REG_H 4 5 #define CYCV_SDRAM_VBASE 0xf0000000 6 #define CYCV_SDRAM_BASE 0x0 7 #define CYCV_SDRAM_SIZE L1_S_SIZE 8 9 #define CYCV_PERIPHERAL_BASE 0xFC000000 10 #define CYCV_PERIPHERAL_SIZE (64 * 1024 * 1024) 11 12 #define CYCV_PERIPHERAL_VBASE CYCV_PERIPHERAL_BASE 13 14 /* Clock manager */ 15 16 #define CYCV_CLKMGR_BASE 0xFFD04000 17 #define CYCV_CLKMGR_SIZE 0x1000 18 19 #define CYCV_CLKMGR_CTRL 0x00 20 #define CYCV_CLKMGR_CTRL_SAFEMODE __BIT(0) 21 #define CYCV_CLKMGR_CTRL_ENSFMDWR __BIT(2) 22 23 #define CYCV_CLKMGR_BYPASS 0x04 24 #define CYCV_CLKMGR_BYPASS_MAINPLL __BIT(0) 25 #define CYCV_CLKMGR_BYPASS_SDRPLL __BIT(1) 26 #define CYCV_CLKMGR_BYPASS_SDRPLLSRC __BIT(2) 27 #define CYCV_CLKMGR_BYPASS_PERPLL __BIT(3) 28 #define CYCV_CLKMGR_BYPASS_PERPLLSRC __BIT(4) 29 30 #define CYCV_CLKMGR_INTER 0x08 31 #define CYCV_CLKMGR_INT_MAINPLLACHIEVED __BIT(0) 32 #define CYCV_CLKMGR_INT_PERPLLACHIEVED __BIT(1) 33 #define CYCV_CLKMGR_INT_SDRPLLACHIEVED __BIT(2) 34 #define CYCV_CLKMGR_INT_MAINPLLLOST __BIT(3) 35 #define CYCV_CLKMGR_INT_PERPLLLOST __BIT(4) 36 #define CYCV_CLKMGR_INT_SDRPLLLOST __BIT(5) 37 #define CYCV_CLKMGR_INTER_MAINPLLLOCKED __BIT(6) 38 #define CYCV_CLKMGR_INTER_PERPLLLOCKED __BIT(7) 39 #define CYCV_CLKMGR_INTER_SDRPLLLOCKED __BIT(8) 40 41 #define CYCV_CLKMGR_INTREN 0x0C 42 /* See CYCV_CLKMGR_INT_* above */ 43 44 #define CYCV_CLKMGR_DBCTRL 0x10 45 #define CYCV_CLKMGR_STAT 0x14 46 47 #define CYCV_CLKMGR_MAIN_PLL_VCO 0x40 48 #define CYCV_CLKMGR_PLL_VCO_NUMER __BITS(3, 15) 49 #define CYCV_CLKMGR_PLL_VCO_DENOM __BITS(16, 21) 50 #define CYCV_CLKMGR_MAIN_PLL_MISC 0x44 51 #define CYCV_CLKMGR_MAIN_PLL_MPUCLK 0x48 52 #define CYCV_CLKMGR_MAIN_PLL_MPUCLK_CNT __BITS(0, 8) 53 #define CYCV_CLKMGR_MAIN_PLL_MAINCLK 0x4C 54 #define CYCV_CLKMGR_MAIN_PLL_MAINCLK_CNT __BITS(0, 8) 55 #define CYCV_CLKMGR_MAIN_PLL_DBGATCLK 0x50 56 #define CYCV_CLKMGR_MAIN_PLL_MAINQSPICLK 0x54 57 #define CYCV_CLKMGR_MAIN_PLL_MAINNANDSDMMCCLK 0x58 58 #define CYCV_CLKMGR_MAIN_PLL_CFGS2FUSER0CLK 0x5C 59 #define CYCV_CLKMGR_MAIN_PLL_EN 0x60 60 #define CYCV_CLKMGR_MAIN_PLL_MAINDIV 0x64 61 #define CYCV_CLKMGR_MAIN_PLL_MAINDIV_L4SP __BITS(7, 9) 62 #define CYCV_CLKMGR_MAIN_PLL_DBGDIV 0x68 63 #define CYCV_CLKMGR_MAIN_PLL_TRACEDIV 0x6C 64 #define CYCV_CLKMGR_MAIN_PLL_L4SRC 0x70 65 #define CYCV_CLKMGR_MAIN_PLL_L4SRC_L4SP __BIT(1) 66 #define CYCV_CLKMGR_MAIN_PLL_L4SRC_L4MP __BIT(0) 67 #define CYCV_CLKMGR_MAIN_PLL_STAT 0x74 68 69 #define CYCV_CLKMGR_PERI_PLL_VCO 0x80 70 #define CYCV_CLKMGR_PERI_PLL_MISC 0x84 71 #define CYCV_CLKMGR_PERI_PLL_EMAC0CLK 0x88 72 #define CYCV_CLKMGR_PERI_PLL_EMAC1CLK 0x8C 73 #define CYCV_CLKMGR_PERI_PLL_PERQSPICLK 0x90 74 #define CYCV_CLKMGR_PERI_PLL_PERNANDSDMMCCLK 0x94 75 #define CYCV_CLKMGR_PERI_PLL_PERBASECLK 0x98 76 #define CYCV_CLKMGR_PERI_PLL_PERBASECLK_CNT __BITS(0, 8) 77 #define CYCV_CLKMGR_PERI_PLL_H2FUSER1CLK 0x9C 78 #define CYCV_CLKMGR_PERI_PLL_EN 0xA0 79 #define CYCV_CLKMGR_PERI_PLL_DIV 0xA4 80 #define CYCV_CLKMGR_PERI_PLL_GPIODIV 0xA8 81 #define CYCV_CLKMGR_PERI_PLL_SRC 0xAC 82 #define CYCV_CLKMGR_PERI_PLL_STAT 0xB0 83 84 #define CYCV_CLKMGR_SDRAM_PLL_VCO 0xC0 85 #define CYCV_CLKMGR_SDRAM_PLL_CTRL 0xC4 86 #define CYCV_CLKMGR_SDRAM_PLL_DDRDQSCLK 0xC8 87 #define CYCV_CLKMGR_SDRAM_PLL_DDR2XDQSCLK 0xCC 88 #define CYCV_CLKMGR_SDRAM_PLL_DDRDQCLK 0xD0 89 #define CYCV_CLKMGR_SDRAM_PLL_S2FUSER2CLK 0xD4 90 #define CYCV_CLKMGR_SDRAM_PLL_EN 0xD8 91 #define CYCV_CLKMGR_SDRAM_PLL_STAT 0xDC 92 93 /* Reset manager */ 94 95 #define CYCV_RSTMGR_BASE 0xFFD05000 96 #define CYCV_RSTMGR_SIZE 0x24 97 98 #define CYCV_RSTMGR_STAT 0x00 99 #define CYCV_RSTMGR_CTRL 0x04 100 #define CYCV_RSTMGR_CTRL_SWCOLDRSTREQ __BIT(0) 101 #define CYCV_RSTMGR_COUNTS 0x08 102 #define CYCV_RSTMGR_MPUMODRST 0x10 103 #define CYCV_RSTMGR_MPUMODRST_CPU1 __BIT(1) 104 #define CYCV_RSTMGR_PERMODRST 0x14 105 #define CYCV_RSTMGR_PER2MODRST 0x18 106 #define CYCV_RSTMGR_BRGMODRST 0x1C 107 #define CYCV_RSTMGR_MISCMODRST 0x20 108 109 /* Snoop Control Unit */ 110 111 #define CYCV_SCU_BASE 0xFFFEC000 112 #define CYCV_SCU_SIZE 0x100 113 114 /* Level 2 Cache */ 115 116 #define CYCV_L2CACHE_BASE 0xFFFEF000 117 #define CYCV_L2CACHE_SIZE 0x1000 118 119 #endif /* _ARM_ALTERA_CYCV_REG_H */ 120