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Searched refs:MemoryLevel (Results 1 – 14 of 14) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_ci_smumgr.c1314 SMU7_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
1323 &(smu_data->smc_state_table.MemoryLevel[i])); in ci_populate_all_memory_levels()
1328 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
1334 smu_data->smc_state_table.MemoryLevel[1].MinVddci = in ci_populate_all_memory_levels()
1335 smu_data->smc_state_table.MemoryLevel[0].MinVddci; in ci_populate_all_memory_levels()
1336 smu_data->smc_state_table.MemoryLevel[1].MinMvdd = in ci_populate_all_memory_levels()
1337 smu_data->smc_state_table.MemoryLevel[0].MinMvdd; in ci_populate_all_memory_levels()
1339 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; in ci_populate_all_memory_levels()
1340 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel); in ci_populate_all_memory_levels()
2775 offsetof(SMU7_Discrete_DpmTable, MemoryLevel); in ci_update_dpm_settings()
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H A Damdgpu_tonga_smumgr.c1102 offsetof(SMU72_Discrete_DpmTable, MemoryLevel); in tonga_populate_all_memory_levels()
1107 smu_data->smc_state_table.MemoryLevel; in tonga_populate_all_memory_levels()
1119 &(smu_data->smc_state_table.MemoryLevel[i])); in tonga_populate_all_memory_levels()
1125 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in tonga_populate_all_memory_levels()
1132 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; in tonga_populate_all_memory_levels()
1133 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel); in tonga_populate_all_memory_levels()
1138 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in tonga_populate_all_memory_levels()
1247 smu_data->smc_state_table.MemoryLevel[0].MinVoltage; in tonga_populate_smc_acpi_level()
3163 offsetof(SMU72_Discrete_DpmTable, MemoryLevel); in tonga_update_dpm_settings()
3165 smu_data->smc_state_table.MemoryLevel; in tonga_update_dpm_settings()
H A Damdgpu_iceland_smumgr.c1359 …rray_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, MemoryLevel); in iceland_populate_all_memory_levels()
1361 SMU71_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel; in iceland_populate_all_memory_levels()
1370 &(smu_data->smc_state_table.MemoryLevel[i])); in iceland_populate_all_memory_levels()
1377 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in iceland_populate_all_memory_levels()
1384 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; in iceland_populate_all_memory_levels()
1385 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel); in iceland_populate_all_memory_levels()
1390 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in iceland_populate_all_memory_levels()
H A Damdgpu_polaris10_smumgr.c159 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel); in polaris10_setup_graphics_level_structure()
1137 offsetof(SMU74_Discrete_DpmTable, MemoryLevel); in polaris10_populate_all_memory_levels()
1141 smu_data->smc_state_table.MemoryLevel; in polaris10_populate_all_memory_levels()
2480 offsetof(SMU74_Discrete_DpmTable, MemoryLevel); in polaris10_update_dpm_settings()
2482 smu_data->smc_state_table.MemoryLevel; in polaris10_update_dpm_settings()
H A Damdgpu_fiji_smumgr.c1234 offsetof(SMU73_Discrete_DpmTable, MemoryLevel); in fiji_populate_all_memory_levels()
1238 smu_data->smc_state_table.MemoryLevel; in fiji_populate_all_memory_levels()
2564 offsetof(SMU73_Discrete_DpmTable, MemoryLevel); in fiji_update_dpm_settings()
2566 smu_data->smc_state_table.MemoryLevel; in fiji_update_dpm_settings()
H A Damdgpu_vegam_smumgr.c1044 offsetof(SMU75_Discrete_DpmTable, MemoryLevel); in vegam_populate_all_memory_levels()
1048 smu_data->smc_state_table.MemoryLevel; in vegam_populate_all_memory_levels()
/netbsd/sys/external/bsd/drm2/dist/drm/radeon/
H A Dsmu7_discrete.h326 SMU7_Discrete_MemoryLevel MemoryLevel [SMU7_MAX_LEVELS_MEMORY]; member
H A Dradeon_ci_dpm.c3334 offsetof(SMU7_Discrete_DpmTable, MemoryLevel); in ci_populate_all_memory_levels()
3337 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
3347 &pi->smc_state_table.MemoryLevel[i]); in ci_populate_all_memory_levels()
3352 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
3356 pi->smc_state_table.MemoryLevel[1].MinVddc = in ci_populate_all_memory_levels()
3357 pi->smc_state_table.MemoryLevel[0].MinVddc; in ci_populate_all_memory_levels()
3358 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = in ci_populate_all_memory_levels()
3359 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; in ci_populate_all_memory_levels()
3362 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); in ci_populate_all_memory_levels()
3368 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
H A Dsmu7_discrete.h327 SMU7_Discrete_MemoryLevel MemoryLevel [SMU7_MAX_LEVELS_MEMORY]; member
H A Dsmu71_discrete.h274 SMU71_Discrete_MemoryLevel MemoryLevel [SMU71_MAX_LEVELS_MEMORY]; member
H A Dsmu73_discrete.h253 SMU73_Discrete_MemoryLevel MemoryLevel [SMU73_MAX_LEVELS_MEMORY]; member
H A Dsmu72_discrete.h269 SMU72_Discrete_MemoryLevel MemoryLevel[SMU72_MAX_LEVELS_MEMORY]; member
H A Dsmu74_discrete.h285 SMU74_Discrete_MemoryLevel MemoryLevel[SMU74_MAX_LEVELS_MEMORY]; member
H A Dsmu75_discrete.h291 SMU75_Discrete_MemoryLevel MemoryLevel [SMU75_MAX_LEVELS_MEMORY]; member