/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrSPE.td | 19 bits<5> RB; 25 let Inst{16-20} = RB; 32 let RB = 0; 46 bits<5> RB; 51 let Inst{16-20} = RB; 60 bits<5> RB; 66 let Inst{16-20} = RB; 73 let RB = 0; 87 bits<5> RB; 94 let Inst{16-20} = RB; [all …]
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/netbsd/external/gpl3/binutils.old/dist/opcodes/ |
H A D | ppc-opc.c | 2387 #define RB RAOPT + 1 macro 2393 #define RSB RB + 1 5753 {"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}}, 5831 {"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}}, 6450 {"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}}, 6707 {"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}}, 7113 {"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}}, 7224 {"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}}, 7250 {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}}, 7254 {"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, [all …]
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H A D | arc-tbl.h | 98 { "acm", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}, 116 { "acm", 0x30280F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, 2738 { "cmp", 0x200C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { 0 }}, 7114 { "fdcmp", 0x30338000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RC }, { 0 }}, 13450 { "mul64", 0x2804003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { RB, RC }, { 0 }}, 16222 { "setcc", 0x20000000, 0xF8C00000, 0, LOGICAL, CD1, { RA, RB, RC }, { C_F }}, 16225 { "setcc", 0x2000003E, 0xF8C0003F, 0, LOGICAL, CD1, { ZA, RB, RC }, { C_F }}, 16231 { "setcc", 0x20400000, 0xF8C00000, 0, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }}, 16234 { "setcc", 0x2040003E, 0xF8C0003F, 0, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }}, 16246 { "setcc", 0x20000F80, 0xF8C00FC0, 0, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }}, [all …]
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H A D | arc-nps400-tbl.h | 80 { "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { 0 }}, 89 { "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { 0 }}, 254 { "csma", 0x382a0000, 0xf8ff8000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, RC }, { 0 }}, 400 { "dctcp", 0x382f0000, 0xf8ff803f, ARC_OPCODE_ARC700, NET, NPS400, { RB, RC }, { 0 }}, 403 { "dcip", 0x38290000, 0xf8ff8000, ARC_OPCODE_ARC700, NET, NPS400, { RA, RB, RC }, { 0 }}, 406 { "dcet", 0x382f0002, 0xf8ff803f, ARC_OPCODE_ARC700, NET, NPS400, { RB, RC }, { 0 }}, 409 { "dcet", 0x38200000, 0xf8ff8000, ARC_OPCODE_ARC700, NET, NPS400, { RA, RB, RC }, { 0 }}, 432 { "tr", 0x38210000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, RC }, { C_F }}, 441 { "tr", 0x3821003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, RC }, { C_F }}, 610 { "sidxalc", 0x385c0040, 0xf8ff0040, ARC_OPCODE_ARC700, BMU, NPS400, { RA, RB }, { 0 }}, [all …]
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H A D | arc-ext-tbl.h | 30 #define ARG_32BIT_RARBRC { RA, RB, RC } 31 #define ARG_32BIT_ZARBRC { ZA, RB, RC } 32 #define ARG_32BIT_RBRBRC { RB, RBdup, RC } 33 #define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 } 34 #define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 } 38 #define ARG_32BIT_RARBLIMM { RA, RB, LIMM } 40 #define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM } 42 #define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM } 50 #define ARG_32BIT_RBRC { RB, RC } 52 #define ARG_32BIT_RBU6 { RB, UIMM6_20 } [all …]
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/netbsd/external/gpl3/gdb/dist/opcodes/ |
H A D | ppc-opc.c | 2725 #define RB RAOPT + 1 macro 2731 #define RSB RB + 1 6315 {"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}}, 6403 {"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}}, 7122 {"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}}, 7468 {"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}}, 7886 {"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}}, 7998 {"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}}, 8024 {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}}, 8028 {"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, [all …]
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H A D | arc-tbl.h | 98 { "acm", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}, 116 { "acm", 0x30280F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, 2738 { "cmp", 0x200C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { 0 }}, 7114 { "fdcmp", 0x30338000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RC }, { 0 }}, 13450 { "mul64", 0x2804003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { RB, RC }, { 0 }}, 16222 { "setcc", 0x20000000, 0xF8C00000, 0, LOGICAL, CD1, { RA, RB, RC }, { C_F }}, 16225 { "setcc", 0x2000003E, 0xF8C0003F, 0, LOGICAL, CD1, { ZA, RB, RC }, { C_F }}, 16231 { "setcc", 0x20400000, 0xF8C00000, 0, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }}, 16234 { "setcc", 0x2040003E, 0xF8C0003F, 0, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }}, 16246 { "setcc", 0x20000F80, 0xF8C00FC0, 0, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }}, [all …]
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H A D | arc-nps400-tbl.h | 80 { "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { 0 }}, 89 { "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { 0 }}, 254 { "csma", 0x382a0000, 0xf8ff8000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, RC }, { 0 }}, 400 { "dctcp", 0x382f0000, 0xf8ff803f, ARC_OPCODE_ARC700, NET, NPS400, { RB, RC }, { 0 }}, 403 { "dcip", 0x38290000, 0xf8ff8000, ARC_OPCODE_ARC700, NET, NPS400, { RA, RB, RC }, { 0 }}, 406 { "dcet", 0x382f0002, 0xf8ff803f, ARC_OPCODE_ARC700, NET, NPS400, { RB, RC }, { 0 }}, 409 { "dcet", 0x38200000, 0xf8ff8000, ARC_OPCODE_ARC700, NET, NPS400, { RA, RB, RC }, { 0 }}, 432 { "tr", 0x38210000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, RC }, { C_F }}, 441 { "tr", 0x3821003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, RC }, { C_F }}, 610 { "sidxalc", 0x385c0040, 0xf8ff0040, ARC_OPCODE_ARC700, BMU, NPS400, { RA, RB }, { 0 }}, [all …]
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H A D | or1k-opc.c | 238 { { MNEM, ' ', OP (RB), 0 } }, 244 { { MNEM, ' ', OP (RB), 0 } }, 490 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 502 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 610 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 622 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 634 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 646 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 658 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 670 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, [all …]
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H A D | arc-ext-tbl.h | 30 #define ARG_32BIT_RARBRC { RA, RB, RC } 31 #define ARG_32BIT_ZARBRC { ZA, RB, RC } 32 #define ARG_32BIT_RBRBRC { RB, RBdup, RC } 33 #define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 } 34 #define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 } 38 #define ARG_32BIT_RARBLIMM { RA, RB, LIMM } 40 #define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM } 42 #define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM } 50 #define ARG_32BIT_RBRC { RB, RC } 52 #define ARG_32BIT_RBU6 { RB, UIMM6_20 } [all …]
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/netbsd/external/gpl3/gdb.old/dist/opcodes/ |
H A D | ppc-opc.c | 2725 #define RB RAOPT + 1 macro 2731 #define RSB RB + 1 6315 {"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}}, 6403 {"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}}, 7122 {"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}}, 7468 {"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}}, 7886 {"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}}, 7998 {"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}}, 8024 {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}}, 8028 {"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, [all …]
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H A D | arc-tbl.h | 98 { "acm", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}, 116 { "acm", 0x30280F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, 2738 { "cmp", 0x200C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { 0 }}, 7114 { "fdcmp", 0x30338000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RC }, { 0 }}, 13450 { "mul64", 0x2804003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { RB, RC }, { 0 }}, 16222 { "setcc", 0x20000000, 0xF8C00000, 0, LOGICAL, CD1, { RA, RB, RC }, { C_F }}, 16225 { "setcc", 0x2000003E, 0xF8C0003F, 0, LOGICAL, CD1, { ZA, RB, RC }, { C_F }}, 16231 { "setcc", 0x20400000, 0xF8C00000, 0, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }}, 16234 { "setcc", 0x2040003E, 0xF8C0003F, 0, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }}, 16246 { "setcc", 0x20000F80, 0xF8C00FC0, 0, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }}, [all …]
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H A D | arc-nps400-tbl.h | 80 { "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { 0 }}, 89 { "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { 0 }}, 254 { "csma", 0x382a0000, 0xf8ff8000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, RC }, { 0 }}, 400 { "dctcp", 0x382f0000, 0xf8ff803f, ARC_OPCODE_ARC700, NET, NPS400, { RB, RC }, { 0 }}, 403 { "dcip", 0x38290000, 0xf8ff8000, ARC_OPCODE_ARC700, NET, NPS400, { RA, RB, RC }, { 0 }}, 406 { "dcet", 0x382f0002, 0xf8ff803f, ARC_OPCODE_ARC700, NET, NPS400, { RB, RC }, { 0 }}, 409 { "dcet", 0x38200000, 0xf8ff8000, ARC_OPCODE_ARC700, NET, NPS400, { RA, RB, RC }, { 0 }}, 432 { "tr", 0x38210000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, RC }, { C_F }}, 441 { "tr", 0x3821003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, RC }, { C_F }}, 610 { "sidxalc", 0x385c0040, 0xf8ff0040, ARC_OPCODE_ARC700, BMU, NPS400, { RA, RB }, { 0 }}, [all …]
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H A D | or1k-opc.c | 238 { { MNEM, ' ', OP (RB), 0 } }, 244 { { MNEM, ' ', OP (RB), 0 } }, 490 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 502 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 610 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 622 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 634 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 646 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 658 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 670 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, [all …]
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/netbsd/external/gpl3/binutils/dist/opcodes/ |
H A D | ppc-opc.c | 3294 #define RB RAOPT + 1 macro 3300 #define RSB RB + 1 6990 {"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}}, 7078 {"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}}, 7806 {"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}}, 8157 {"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}}, 8584 {"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}}, 8696 {"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}}, 8722 {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}}, 8726 {"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, [all …]
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H A D | arc-tbl.h | 98 { "acm", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}, 116 { "acm", 0x30280F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, 2738 { "cmp", 0x200C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { 0 }}, 7114 { "fdcmp", 0x30338000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RC }, { 0 }}, 13450 { "mul64", 0x2804003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { RB, RC }, { 0 }}, 16222 { "setcc", 0x20000000, 0xF8C00000, 0, LOGICAL, CD1, { RA, RB, RC }, { C_F }}, 16225 { "setcc", 0x2000003E, 0xF8C0003F, 0, LOGICAL, CD1, { ZA, RB, RC }, { C_F }}, 16231 { "setcc", 0x20400000, 0xF8C00000, 0, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }}, 16234 { "setcc", 0x2040003E, 0xF8C0003F, 0, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }}, 16246 { "setcc", 0x20000F80, 0xF8C00FC0, 0, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }}, [all …]
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H A D | arc-nps400-tbl.h | 80 { "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { 0 }}, 89 { "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { 0 }}, 254 { "csma", 0x382a0000, 0xf8ff8000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, RC }, { 0 }}, 400 { "dctcp", 0x382f0000, 0xf8ff803f, ARC_OPCODE_ARC700, NET, NPS400, { RB, RC }, { 0 }}, 403 { "dcip", 0x38290000, 0xf8ff8000, ARC_OPCODE_ARC700, NET, NPS400, { RA, RB, RC }, { 0 }}, 406 { "dcet", 0x382f0002, 0xf8ff803f, ARC_OPCODE_ARC700, NET, NPS400, { RB, RC }, { 0 }}, 409 { "dcet", 0x38200000, 0xf8ff8000, ARC_OPCODE_ARC700, NET, NPS400, { RA, RB, RC }, { 0 }}, 432 { "tr", 0x38210000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, RC }, { C_F }}, 441 { "tr", 0x3821003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, RC }, { C_F }}, 610 { "sidxalc", 0x385c0040, 0xf8ff0040, ARC_OPCODE_ARC700, BMU, NPS400, { RA, RB }, { 0 }}, [all …]
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H A D | or1k-opc.c | 238 { { MNEM, ' ', OP (RB), 0 } }, 244 { { MNEM, ' ', OP (RB), 0 } }, 490 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 502 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 610 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 622 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 634 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 646 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 658 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 670 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, [all …]
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H A D | arc-ext-tbl.h | 30 #define ARG_32BIT_RARBRC { RA, RB, RC } 31 #define ARG_32BIT_ZARBRC { ZA, RB, RC } 32 #define ARG_32BIT_RBRBRC { RB, RBdup, RC } 33 #define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 } 34 #define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 } 38 #define ARG_32BIT_RARBLIMM { RA, RB, LIMM } 40 #define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM } 42 #define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM } 50 #define ARG_32BIT_RBRC { RB, RC } 52 #define ARG_32BIT_RBU6 { RB, UIMM6_20 } [all …]
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/netbsd/sys/external/bsd/compiler_rt/dist/lib/sanitizer_common/tests/ |
H A D | sanitizer_ring_buffer_test.cc | 37 RingBuffer<T> *RB; in TestRB() local 40 RB = RingBuffer<T>::New(Size); in TestRB() 41 EXPECT_EQ(RB->size(), Size); in TestRB() 42 RB->Delete(); in TestRB() 45 RB = RingBuffer<T>::New(4); in TestRB() 46 EXPECT_EQ(RB->size(), 4U); in TestRB() 51 EXPECT_EQ((int64_t)(*RB)[3], (int64_t)a3); in TestRB() 53 RB->push(T(1)); EXPECT_RING_BUFFER(1, 0, 0, 0); in TestRB() 54 RB->push(T(2)); EXPECT_RING_BUFFER(2, 1, 0, 0); in TestRB() 55 RB->push(T(3)); EXPECT_RING_BUFFER(3, 2, 1, 0); in TestRB() [all …]
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/netbsd/external/gpl3/gdb/dist/sim/microblaze/ |
H A D | microblaze.isa | 32 RD = RA + RB; 63 RD = RA + RB; 349 PC += RB; 363 PC += RB; 370 PC = RB; 384 PC = RB; 392 PC = RB; 400 PC += RB; 410 PC += RB; 421 PC += RB; [all …]
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/netbsd/external/gpl3/gdb.old/dist/sim/microblaze/ |
H A D | microblaze.isa | 32 RD = RA + RB; 63 RD = RA + RB; 349 PC += RB; 363 PC += RB; 370 PC = RB; 384 PC = RB; 392 PC = RB; 400 PC += RB; 410 PC += RB; 421 PC += RB; [all …]
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/netbsd/external/gpl3/gdb/dist/sim/ppc/ |
H A D | e500.igen | 29 :cache:e500::signed_word *:rBh:RB:(cpu_registers(processor)->e500.gprh + RB) 383 0.4,6.RS,11.RA,16.RB,21.512:X:e500:evaddw %RS,%RA,%RB:Vector Add Word 460 0.4,6.RS,11.RA,16.RB,21.529:X:e500:evand %RS,%RA,%RB:Vector AND 467 0.4,6.RS,11.RA,16.RB,21.535:X:e500:evor %RS,%RA,%RB:Vector OR 474 0.4,6.RS,11.RA,16.RB,21.534:X:e500:evxor %RS,%RA,%RB:Vector XOR 481 0.4,6.RS,11.RA,16.RB,21.542:X:e500:evnand %RS,%RA,%RB:Vector NAND 488 0.4,6.RS,11.RA,16.RB,21.536:X:e500:evnor %RS,%RA,%RB:Vector NOR 495 0.4,6.RS,11.RA,16.RB,21.537:X:e500:eveqv %RS,%RA,%RB:Vector Equivalent 536 0.4,6.RS,11.RA,16.RB,21.548:X:e500:evslw %RS,%RA,%RB:Vector Shift Left Word 619 0.4,6.RS,11.RA,16.RB,21.556:X:e500:evmergehi %RS,%RA,%RB:Vector Merge Hi [all …]
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/netbsd/external/gpl3/gdb.old/dist/sim/ppc/ |
H A D | e500.igen | 29 :cache:e500::signed_word *:rBh:RB:(cpu_registers(processor)->e500.gprh + RB) 383 0.4,6.RS,11.RA,16.RB,21.512:X:e500:evaddw %RS,%RA,%RB:Vector Add Word 460 0.4,6.RS,11.RA,16.RB,21.529:X:e500:evand %RS,%RA,%RB:Vector AND 467 0.4,6.RS,11.RA,16.RB,21.535:X:e500:evor %RS,%RA,%RB:Vector OR 474 0.4,6.RS,11.RA,16.RB,21.534:X:e500:evxor %RS,%RA,%RB:Vector XOR 481 0.4,6.RS,11.RA,16.RB,21.542:X:e500:evnand %RS,%RA,%RB:Vector NAND 488 0.4,6.RS,11.RA,16.RB,21.536:X:e500:evnor %RS,%RA,%RB:Vector NOR 495 0.4,6.RS,11.RA,16.RB,21.537:X:e500:eveqv %RS,%RA,%RB:Vector Equivalent 536 0.4,6.RS,11.RA,16.RB,21.548:X:e500:evslw %RS,%RA,%RB:Vector Shift Left Word 619 0.4,6.RS,11.RA,16.RB,21.556:X:e500:evmergehi %RS,%RA,%RB:Vector Merge Hi [all …]
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/netbsd/external/apache2/llvm/dist/clang/lib/Rewrite/ |
H A D | HTMLRewrite.cpp | 62 RB.InsertTextAfter(B, StartTag); in HighlightRange() 63 RB.InsertTextBefore(E, EndTag); in HighlightRange() 96 RB.InsertTextAfter(i, StartTag); in HighlightRange() 133 RB.ReplaceText(FilePos, 1, "<hr>"); in EscapeText() 142 RB.ReplaceText(FilePos, 1, in EscapeText() 151 RB.ReplaceText(FilePos, 1, "<"); in EscapeText() 156 RB.ReplaceText(FilePos, 1, ">"); in EscapeText() 220 RB.InsertTextBefore(B, OS.str()); in AddLineNumber() 222 RB.InsertTextBefore(B, OS.str()); in AddLineNumber() 223 RB.InsertTextBefore(E, "</td></tr>"); in AddLineNumber() [all …]
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