/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
H A D | amdgpu_vcn_v2_5.c | 857 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start_dpg_mode() 1037 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start() 1251 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_sriov_start()
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H A D | amdgpu_uvd_v5_0.c | 399 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v5_0_start()
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H A D | amdgpu_vcn_v2_0.c | 844 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start_dpg_mode() 1005 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start()
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H A D | amdgpu_vcn_v1_0.c | 908 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start_spg_mode() 1066 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start_dpg_mode()
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H A D | amdgpu_uvd_v7_0.c | 902 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size); in uvd_v7_0_sriov_start() 1069 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v7_0_start()
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H A D | amdgpu_uvd_v6_0.c | 817 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v6_0_start()
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H A D | sid.h | 1278 #define RB_BUFSZ(x) ((x) << 0) macro
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H A D | amdgpu_gfx_v10_0.c | 2791 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_cp_gfx_resume() 2832 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_cp_gfx_resume() 3036 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_gfx_mqd_init()
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H A D | amdgpu_gfx_v9_0.c | 3192 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v9_0_cp_gfx_resume()
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H A D | amdgpu_gfx_v8_0.c | 4282 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v8_0_cp_gfx_resume()
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/netbsd/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | rv770d.h | 352 #define RB_BUFSZ(x) ((x) << 0) macro
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H A D | nid.h | 487 #define RB_BUFSZ(x) ((x) << 0) macro
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H A D | sid.h | 1249 #define RB_BUFSZ(x) ((x) << 0) macro
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H A D | cikd.h | 1305 #define RB_BUFSZ(x) ((x) << 0) macro
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H A D | radeon_rv770.c | 1110 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in rv770_cp_load_microcode()
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H A D | evergreend.h | 479 #define RB_BUFSZ(x) ((x) << 0) macro
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H A D | r600d.h | 198 #define RB_BUFSZ(x) ((x) << 0) macro
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H A D | radeon_r600.c | 2690 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in r600_cp_load_microcode()
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H A D | radeon_evergreen.c | 2985 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in evergreen_cp_load_microcode()
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