/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMInstPrinter.h | 29 const MCSubtargetInfo &STI, raw_ostream &O) override; 35 const MCSubtargetInfo &STI, raw_ostream &O); 40 const MCSubtargetInfo &STI, 48 const MCSubtargetInfo &STI, raw_ostream &O) { in printOperand() argument 49 printOperand(MI, OpNum, STI, O); in printOperand() 99 const MCSubtargetInfo &STI, 121 printAdrLabelOperand<scale>(MI, OpNum, STI, O); in printAdrLabelOperand() 132 const MCSubtargetInfo &STI, 172 const MCSubtargetInfo &STI, raw_ostream &O); 223 printThumbLdrLabelOperand(MI, OpNum, STI, O); in printThumbLdrLabelOperand() [all …]
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H A D | ARMTargetStreamer.cpp | 120 if (STI.getCPU() == "xscale") in getArchForCPU() 123 if (STI.hasFeature(ARM::HasV8Ops)) { in getArchForCPU() 132 if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP)) in getArchForCPU() 141 else if (STI.hasFeature(ARM::HasV6Ops)) in getArchForCPU() 197 if (isV8M(STI)) { in emitTargetAttributes() 221 if (STI.hasFeature(ARM::HasV8Ops)) in emitTargetAttributes() 257 if (STI.hasFeature(ARM::FeatureVFP2_SP) && !STI.hasFeature(ARM::FeatureFP64)) in emitTargetAttributes() 261 if (STI.hasFeature(ARM::FeatureFP16)) in emitTargetAttributes() 264 if (STI.hasFeature(ARM::FeatureMP)) in emitTargetAttributes() 278 if (STI.hasFeature(ARM::FeatureHWDivARM) && !STI.hasFeature(ARM::HasV8Ops)) in emitTargetAttributes() [all …]
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H A D | ARMMCCodeEmitter.cpp | 68 return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2]; in isThumb2() 483 if (isThumb2(STI)) { in NEONThumb2DataIPostEncoder() 503 if (isThumb2(STI)) { in NEONThumb2LoadStorePostEncoder() 517 if (isThumb2(STI)) { in NEONThumb2DupPostEncoder() 530 if (isThumb2(STI)) { in NEONThumb2V8PostEncoder() 542 if (isThumb2(STI)) { in VFPThumb2PostEncoder() 741 if (isThumb2(STI)) in getBranchTargetOpValue() 989 assert(!isThumb(STI) && !isThumb2(STI) && in getAddrModeImm12OpValue() 1000 if (isThumb2(STI)) in getAddrModeImm12OpValue() 1434 if (isThumb2(STI)) in getAddrMode5OpValue() [all …]
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H A D | ARMInstPrinter.cpp | 157 printRegisterList(MI, 4, STI, O); in printInst() 186 printRegisterList(MI, 4, STI, O); in printInst() 212 printRegisterList(MI, 4, STI, O); in printInst() 247 printRegisterList(MI, 3, STI, O); in printInst() 477 printOperand(MI, Op, STI, O); in printAddrMode2Operand() 550 printOperand(MI, Op, STI, O); in printAddrMode3Operand() 657 printOperand(MI, OpNum, STI, O); in printAddrMode5Operand() 681 printOperand(MI, OpNum, STI, O); in printAddrMode5FP16Operand() 1094 printOperand(MI, Op, STI, O); in printThumbAddrModeRROperand() 1116 printOperand(MI, Op, STI, O); in printThumbAddrModeImm5SOperand() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | AMDGPUInstPrinter.h | 72 const MCSubtargetInfo &STI, raw_ostream &O); 90 const MCSubtargetInfo &STI, raw_ostream &O); 92 const MCSubtargetInfo &STI, raw_ostream &O); 96 const MCSubtargetInfo &STI, raw_ostream &O); 98 const MCSubtargetInfo &STI, raw_ostream &O); 121 printOperand(MI, OpNum, STI, O); in printOperand() 138 const MCSubtargetInfo &STI, raw_ostream &O); 151 const MCSubtargetInfo &STI, raw_ostream &O); 153 const MCSubtargetInfo &STI, raw_ostream &O); 155 const MCSubtargetInfo &STI, raw_ostream &O); [all …]
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H A D | AMDGPUInstPrinter.cpp | 155 if (AMDGPU::isGFX10Plus(STI)) { in printFlatOffset() 309 if (AMDGPU::isGFX10Plus(STI)) { in printSymbolicFormat() 320 if (isValidDfmtNfmt(Val, STI)) { in printSymbolicFormat() 385 printOperand(MI, OpNo, STI, O); in printVOPDst() 410 if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI)) in printVINTRPDst() 415 printOperand(MI, OpNo, STI, O); in printVINTRPDst() 468 printImmediate16(Lo16, STI, O); in printImmediateV216() 793 if (!AMDGPU::isGFX10Plus(STI)) in printDPP8() 879 if (AMDGPU::isGFX90A(STI)) { in printDPPCtrl() 1204 printOperand(MI, OpNo, STI, O); in printMemOperand() [all …]
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H A D | SIMCCodeEmitter.cpp | 34 const MCSubtargetInfo &STI) const; 135 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) in getLit16Encoding() 171 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) in getLit32Encoding() 207 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) in getLit64Encoding() 244 return getLit32Encoding(static_cast<uint32_t>(Imm), STI); in getLitEncoding() 251 return getLit64Encoding(static_cast<uint64_t>(Imm), STI); in getLitEncoding() 277 uint32_t Encoding = getLit16Encoding(Lo16, STI); in getLitEncoding() 335 Fixups, STI)); in encodeInstruction() 353 if (getLitEncoding(Op, Desc.OpInfo[i], STI) != 255) in encodeInstruction() 389 return getMachineOpValue(MI, MO, Fixups, STI); in getSOPPBrEncoding() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64InstPrinter.h | 29 const MCSubtargetInfo &STI, raw_ostream &O) override; 40 const MCSubtargetInfo &STI, 51 bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI, 77 const MCSubtargetInfo &STI, raw_ostream &O); 82 const MCSubtargetInfo &STI, raw_ostream &O); 101 const MCSubtargetInfo &STI, raw_ostream &O); 128 const MCSubtargetInfo &STI, raw_ostream &O); 178 const MCSubtargetInfo &STI, 190 const MCSubtargetInfo &STI, raw_ostream &O); 194 const MCSubtargetInfo &STI, raw_ostream &O); [all …]
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H A D | AArch64MCCodeEmitter.cpp | 64 const MCSubtargetInfo &STI) const; 167 const MCSubtargetInfo &STI) const; 170 const MCSubtargetInfo &STI) const; 173 const MCSubtargetInfo &STI) const; 180 const MCSubtargetInfo &STI) const; 184 const MCSubtargetInfo &STI) const; 297 const MCSubtargetInfo &STI) const { in getCondBranchTargetOpValue() 367 const MCSubtargetInfo &STI) const { in getTestBranchTargetOpValue() 441 const MCSubtargetInfo &STI) const { in getFixedPointScaleOpValue() 551 const MCSubtargetInfo &STI) const { in getMoveVecShifterOpValue() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.h | 35 bool isMicroMips(const MCSubtargetInfo &STI) const; 36 bool isMips32r6(const MCSubtargetInfo &STI) const; 58 const MCSubtargetInfo &STI) const; 65 const MCSubtargetInfo &STI) const; 78 const MCSubtargetInfo &STI) const; 82 const MCSubtargetInfo &STI) const; 182 const MCSubtargetInfo &STI) const; 186 const MCSubtargetInfo &STI) const; 191 const MCSubtargetInfo &STI) const; 245 const MCSubtargetInfo &STI) const; [all …]
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H A D | MipsMCCodeEmitter.cpp | 125 return STI.getFeatureBits()[Mips::FeatureMips32r6]; in isMips32r6() 140 emitInstruction(Val >> 16, 2, STI, OS); in emitInstruction() 141 emitInstruction(Val, 2, STI, OS); in emitInstruction() 155 const MCSubtargetInfo &STI) const in encodeInstruction() 194 if (isMicroMips(STI)) { in encodeInstruction() 195 if (isMips32r6(STI)) { in encodeInstruction() 229 emitInstruction(Binary, Size, STI, OS); in encodeInstruction() 457 const MCSubtargetInfo &STI) const { in getBranchTarget26OpValueMM() 591 const MCSubtargetInfo &STI) const { in getExprOpValue() 748 return getExprOpValue(MO.getExpr(),Fixups, STI); in getMachineOpValue() [all …]
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H A D | MipsTargetStreamer.cpp | 135 const MCSubtargetInfo *STI) { in emitDirectiveCpRestore() argument 264 STI); in emitAddu() 287 if (isMicroMips(STI)) in emitNop() 303 const MCSubtargetInfo *STI) { in emitStoreWithImmOffset() argument 686 const MCSubtargetInfo *STI) { in emitDirectiveCpRestore() argument 788 : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) { in MipsTargetELFStreamer() 1205 const MCSubtargetInfo *STI) { in emitDirectiveCpRestore() argument 1220 STI); in emitDirectiveCpRestore() 1260 &STI); in emitDirectiveCpsetup() 1277 &STI); in emitDirectiveCpsetup() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/ |
H A D | AMDGPUBaseInfo.cpp | 92 if (STI && STI->getTargetTriple().getOS() != Triple::AMDHSA) in getHsaAbiVersion() 127 return isHsaAbiVersion3(STI) || isHsaAbiVersion4(STI); in isHsaAbiVersion3Or4() 324 : STI(STI), XnackSetting(TargetIDSetting::Any), in AMDGPUTargetID() 539 if (isGFX10Plus(*STI) && STI->getFeatureBits().test(FeatureCuMode)) in getEUsPerCU() 1008 if (isSI(STI) || isCI(STI) || isVI(STI)) in getLastSymbolicHwreg() 1012 else if (isGFX10(STI) && !isGFX10_BEncoding(STI)) in getLastSymbolicHwreg() 1135 if (isSI(STI) || isCI(STI)) in getNfmtLookupTable() 1137 if (isVI(STI) || isGFX9(STI)) in getNfmtLookupTable() 1231 return isVI(STI) || isGFX9Plus(STI); in isValidMsgId() 1437 return isGFX9(STI) || isGFX10Plus(STI); in isGFX9Plus() [all …]
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H A D | AMDGPUBaseInfo.h | 43 bool isHsaAbiVersion2(const MCSubtargetInfo *STI); 87 const MCSubtargetInfo &STI; 433 const MCSubtargetInfo *STI); 725 bool hasXNACK(const MCSubtargetInfo &STI); 729 bool hasG16(const MCSubtargetInfo &STI); 732 bool isSI(const MCSubtargetInfo &STI); 733 bool isCI(const MCSubtargetInfo &STI); 734 bool isVI(const MCSubtargetInfo &STI); 735 bool isGFX9(const MCSubtargetInfo &STI); 737 bool isGFX10(const MCSubtargetInfo &STI); [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCInstPrinter.h | 36 const MCSubtargetInfo &STI, raw_ostream &O) override; 41 const MCSubtargetInfo &STI, raw_ostream &O); 45 const MCSubtargetInfo &STI, raw_ostream &OS); 56 const MCSubtargetInfo &STI, raw_ostream &O); 59 const MCSubtargetInfo &STI, raw_ostream &O); 61 const MCSubtargetInfo &STI, raw_ostream &O); 63 const MCSubtargetInfo &STI, raw_ostream &O); 65 const MCSubtargetInfo &STI, raw_ostream &O); 67 const MCSubtargetInfo &STI, raw_ostream &O); 99 const MCSubtargetInfo &STI, raw_ostream &O); [all …]
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H A D | PPCMCCodeEmitter.h | 40 const MCSubtargetInfo &STI) const; 43 const MCSubtargetInfo &STI) const; 49 const MCSubtargetInfo &STI) const; 52 const MCSubtargetInfo &STI) const; 55 const MCSubtargetInfo &STI, 65 const MCSubtargetInfo &STI) const; 68 const MCSubtargetInfo &STI) const; 80 const MCSubtargetInfo &STI) const; 83 const MCSubtargetInfo &STI) const; 92 const MCSubtargetInfo &STI) const; [all …]
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H A D | PPCMCCodeEmitter.cpp | 45 const MCSubtargetInfo &STI) const { in getDirectBrEncoding() 49 return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding() 74 const MCSubtargetInfo &STI) const { in getAbsDirectBrEncoding() 87 const MCSubtargetInfo &STI) const { in getAbsCondBrEncoding() 126 return getMachineOpValue(MI, MO, Fixups, STI); in getImm34Encoding() 137 return getImm34Encoding(MI, OpNo, Fixups, STI, in getImm34EncodingNoPCRel() 145 return getImm34Encoding(MI, OpNo, Fixups, STI, in getImm34EncodingPCRel() 387 const Triple &TT = STI.getTargetTriple(); in getTLSRegEncoding() 401 return getDirectBrEncoding(MI, OpNo, Fixups, STI); in getTLSCallEncoding() 432 const MCSubtargetInfo &STI) const { in getMachineOpValue() [all …]
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H A D | PPCInstPrinter.cpp | 74 printOperand(MI, 0, STI, O); in printInst() 76 printOperand(MI, 2, STI, O); in printInst() 78 printOperand(MI, 1, STI, O); in printInst() 127 printOperand(MI, 0, STI, O); in printInst() 129 printOperand(MI, 1, STI, O); in printInst() 144 printOperand(MI, 0, STI, O); in printInst() 146 printOperand(MI, 1, STI, O); in printInst() 174 printOperand(MI, 1, STI, O); in printInst() 176 printOperand(MI, 2, STI, O); in printInst() 201 printOperand(MI, 1, STI, O); in printInst() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCCodeEmitter.cpp | 61 const MCSubtargetInfo &STI) const; 157 const MCSubtargetInfo &STI) const { in encodeInstruction() 161 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction() 174 const MCSubtargetInfo &STI) const { in getMachineOpValue() 185 const MCSubtargetInfo &STI) const { in getBDAddr12Encoding() 195 const MCSubtargetInfo &STI) const { in getBDAddr20Encoding() 205 const MCSubtargetInfo &STI) const { in getBDXAddr12Encoding() 216 const MCSubtargetInfo &STI) const { in getBDXAddr20Encoding() 228 const MCSubtargetInfo &STI) const { in getBDLAddr12Len4Encoding() 250 const MCSubtargetInfo &STI) const { in getBDRAddr12Encoding() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/ |
H A D | RISCVTargetStreamer.cpp | 41 if (STI.hasFeature(RISCV::FeatureRV32E)) in emitTargetAttributes() 47 if (STI.hasFeature(RISCV::Feature64Bit)) in emitTargetAttributes() 49 if (STI.hasFeature(RISCV::FeatureRV32E)) in emitTargetAttributes() 67 if (STI.hasFeature(RISCV::FeatureExtZfh)) in emitTargetAttributes() 69 if (STI.hasFeature(RISCV::FeatureExtZba)) in emitTargetAttributes() 71 if (STI.hasFeature(RISCV::FeatureExtZbb)) in emitTargetAttributes() 73 if (STI.hasFeature(RISCV::FeatureExtZbc)) in emitTargetAttributes() 75 if (STI.hasFeature(RISCV::FeatureExtZbe)) in emitTargetAttributes() 77 if (STI.hasFeature(RISCV::FeatureExtZbf)) in emitTargetAttributes() 79 if (STI.hasFeature(RISCV::FeatureExtZbm)) in emitTargetAttributes() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/VE/MCTargetDesc/ |
H A D | VEInstPrinter.cpp | 83 printOperand(MI, OpNum, STI, O); in printMemASXOperand() 85 printOperand(MI, OpNum + 1, STI, O); in printMemASXOperand() 93 printOperand(MI, OpNum + 2, STI, O); in printMemASXOperand() 116 printOperand(MI, OpNum, STI, O); in printMemASXOperand() 127 printOperand(MI, OpNum, STI, O); in printMemASOperandASX() 129 printOperand(MI, OpNum + 1, STI, O); in printMemASOperandASX() 148 printOperand(MI, OpNum, STI, O); in printMemASOperandASX() 158 printOperand(MI, OpNum, STI, O); in printMemASOperandRRM() 179 printOperand(MI, OpNum, STI, O); in printMemASOperandRRM() 189 printOperand(MI, OpNum, STI, O); in printMemASOperandHM() [all …]
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H A D | VEMCCodeEmitter.cpp | 54 const MCSubtargetInfo &STI) const override; 60 const MCSubtargetInfo &STI) const; 66 const MCSubtargetInfo &STI) const; 70 const MCSubtargetInfo &STI) const; 73 const MCSubtargetInfo &STI) const; 76 const MCSubtargetInfo &STI) const; 89 const MCSubtargetInfo &STI) const { in encodeInstruction() 93 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction() 131 return getMachineOpValue(MI, MO, Fixups, STI); in getBranchTargetOpValue() 140 const MCSubtargetInfo &STI) const { in getCCOpValue() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
H A D | VEAsmPrinter.cpp | 88 OutStreamer.emitInstruction(SICInst, STI); in emitSIC() 100 OutStreamer.emitInstruction(BSICInst, STI); in emitBSIC() 112 OutStreamer.emitInstruction(LEAInst, STI); in emitLEAzzi() 136 OutStreamer.emitInstruction(LEAInst, STI); in emitLEAzii() 159 OutStreamer.emitInstruction(Inst, STI); in emitBinary() 174 emitLEAzzi(OutStreamer, lo, RD, STI); in emitHiLo() 176 emitANDrm(OutStreamer, RD, M032, RD, STI); in emitHiLo() 177 emitLEASLzzi(OutStreamer, hi, RD, STI); in emitHiLo() 216 emitSIC(*OutStreamer, RegPLT, STI); in lowerGETGOTAndEmitMCInsts() 264 emitSIC(*OutStreamer, RegPLT, STI); in lowerGETFunPLTAndEmitMCInsts() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcInstPrinter.cpp | 49 if (!printAliasInstr(MI, Address, STI, O) && in printInst() 50 !printSparcAliasInstr(MI, STI, O)) in printInst() 51 printInstruction(MI, Address, STI, O); in printInst() 77 O << "\tjmp "; printMemOperand(MI, 1, STI, O); in printSparcAliasInstr() 86 if (isV9(STI) in printSparcAliasInstr() 101 printOperand(MI, 1, STI, O); in printSparcAliasInstr() 103 printOperand(MI, 2, STI, O); in printSparcAliasInstr() 146 printOperand(MI, opNum, STI, O); in printMemOperand() 148 printOperand(MI, opNum + 1, STI, O); in printMemOperand() 157 printOperand(MI, opNum, STI, O); in printMemOperand() [all …]
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H A D | SparcMCCodeEmitter.cpp | 71 const MCSubtargetInfo &STI) const; 74 const MCSubtargetInfo &STI) const; 80 const MCSubtargetInfo &STI) const; 103 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction() 118 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI); in encodeInstruction() 129 const MCSubtargetInfo &STI) const { in getMachineOpValue() 186 const MCSubtargetInfo &STI) const { in getCallTargetOpValue() 213 const MCSubtargetInfo &STI) const { in getBranchTargetOpValue() 216 return getMachineOpValue(MI, MO, Fixups, STI); in getBranchTargetOpValue() 229 return getMachineOpValue(MI, MO, Fixups, STI); in getBranchPredTargetOpValue() [all …]
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