1 //===-- SparcMCCodeEmitter.cpp - Convert Sparc code to machine code -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SparcMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MCTargetDesc/SparcFixupKinds.h"
14 #include "SparcMCExpr.h"
15 #include "SparcMCTargetDesc.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCFixup.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCObjectFileInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MCSymbol.h"
29 #include "llvm/MC/SubtargetFeature.h"
30 #include "llvm/Support/Casting.h"
31 #include "llvm/Support/Endian.h"
32 #include "llvm/Support/EndianStream.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include <cassert>
36 #include <cstdint>
37
38 using namespace llvm;
39
40 #define DEBUG_TYPE "mccodeemitter"
41
42 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
43
44 namespace {
45
46 class SparcMCCodeEmitter : public MCCodeEmitter {
47 const MCInstrInfo &MCII;
48 MCContext &Ctx;
49
50 public:
SparcMCCodeEmitter(const MCInstrInfo & mcii,MCContext & ctx)51 SparcMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
52 : MCII(mcii), Ctx(ctx) {}
53 SparcMCCodeEmitter(const SparcMCCodeEmitter &) = delete;
54 SparcMCCodeEmitter &operator=(const SparcMCCodeEmitter &) = delete;
55 ~SparcMCCodeEmitter() override = default;
56
57 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
58 SmallVectorImpl<MCFixup> &Fixups,
59 const MCSubtargetInfo &STI) const override;
60
61 // getBinaryCodeForInstr - TableGen'erated function for getting the
62 // binary encoding for an instruction.
63 uint64_t getBinaryCodeForInstr(const MCInst &MI,
64 SmallVectorImpl<MCFixup> &Fixups,
65 const MCSubtargetInfo &STI) const;
66
67 /// getMachineOpValue - Return binary encoding of operand. If the machine
68 /// operand requires relocation, record the relocation and return zero.
69 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
70 SmallVectorImpl<MCFixup> &Fixups,
71 const MCSubtargetInfo &STI) const;
72 unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
73 SmallVectorImpl<MCFixup> &Fixups,
74 const MCSubtargetInfo &STI) const;
75 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
76 SmallVectorImpl<MCFixup> &Fixups,
77 const MCSubtargetInfo &STI) const;
78 unsigned getSImm13OpValue(const MCInst &MI, unsigned OpNo,
79 SmallVectorImpl<MCFixup> &Fixups,
80 const MCSubtargetInfo &STI) const;
81 unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
82 SmallVectorImpl<MCFixup> &Fixups,
83 const MCSubtargetInfo &STI) const;
84 unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
85 SmallVectorImpl<MCFixup> &Fixups,
86 const MCSubtargetInfo &STI) const;
87
88 private:
89 FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const;
90 void
91 verifyInstructionPredicates(const MCInst &MI,
92 const FeatureBitset &AvailableFeatures) const;
93 };
94
95 } // end anonymous namespace
96
encodeInstruction(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const97 void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
98 SmallVectorImpl<MCFixup> &Fixups,
99 const MCSubtargetInfo &STI) const {
100 verifyInstructionPredicates(MI,
101 computeAvailableFeatures(STI.getFeatureBits()));
102
103 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
104 support::endian::write(OS, Bits,
105 Ctx.getAsmInfo()->isLittleEndian() ? support::little
106 : support::big);
107 unsigned tlsOpNo = 0;
108 switch (MI.getOpcode()) {
109 default: break;
110 case SP::TLS_CALL: tlsOpNo = 1; break;
111 case SP::TLS_ADDrr:
112 case SP::TLS_ADDXrr:
113 case SP::TLS_LDrr:
114 case SP::TLS_LDXrr: tlsOpNo = 3; break;
115 }
116 if (tlsOpNo != 0) {
117 const MCOperand &MO = MI.getOperand(tlsOpNo);
118 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI);
119 assert(op == 0 && "Unexpected operand value!");
120 (void)op; // suppress warning.
121 }
122
123 ++MCNumEmitted; // Keep track of the # of mi's emitted.
124 }
125
126 unsigned SparcMCCodeEmitter::
getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const127 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
128 SmallVectorImpl<MCFixup> &Fixups,
129 const MCSubtargetInfo &STI) const {
130 if (MO.isReg())
131 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
132
133 if (MO.isImm())
134 return MO.getImm();
135
136 assert(MO.isExpr());
137 const MCExpr *Expr = MO.getExpr();
138 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
139 MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind();
140 Fixups.push_back(MCFixup::create(0, Expr, Kind));
141 return 0;
142 }
143
144 int64_t Res;
145 if (Expr->evaluateAsAbsolute(Res))
146 return Res;
147
148 llvm_unreachable("Unhandled expression!");
149 return 0;
150 }
151
152 unsigned
getSImm13OpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const153 SparcMCCodeEmitter::getSImm13OpValue(const MCInst &MI, unsigned OpNo,
154 SmallVectorImpl<MCFixup> &Fixups,
155 const MCSubtargetInfo &STI) const {
156 const MCOperand &MO = MI.getOperand(OpNo);
157
158 if (MO.isImm())
159 return MO.getImm();
160
161 assert(MO.isExpr() &&
162 "getSImm13OpValue expects only expressions or an immediate");
163
164 const MCExpr *Expr = MO.getExpr();
165
166 // Constant value, no fixup is needed
167 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
168 return CE->getValue();
169
170 MCFixupKind Kind;
171 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
172 Kind = MCFixupKind(SExpr->getFixupKind());
173 } else {
174 bool IsPic = Ctx.getObjectFileInfo()->isPositionIndependent();
175 Kind = IsPic ? MCFixupKind(Sparc::fixup_sparc_got13)
176 : MCFixupKind(Sparc::fixup_sparc_13);
177 }
178
179 Fixups.push_back(MCFixup::create(0, Expr, Kind));
180 return 0;
181 }
182
183 unsigned SparcMCCodeEmitter::
getCallTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const184 getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
185 SmallVectorImpl<MCFixup> &Fixups,
186 const MCSubtargetInfo &STI) const {
187 const MCOperand &MO = MI.getOperand(OpNo);
188 const MCExpr *Expr = MO.getExpr();
189 const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr);
190
191 if (MI.getOpcode() == SP::TLS_CALL) {
192 // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in
193 // encodeInstruction.
194 #ifndef NDEBUG
195 // Verify that the callee is actually __tls_get_addr.
196 assert(SExpr && SExpr->getSubExpr()->getKind() == MCExpr::SymbolRef &&
197 "Unexpected expression in TLS_CALL");
198 const MCSymbolRefExpr *SymExpr = cast<MCSymbolRefExpr>(SExpr->getSubExpr());
199 assert(SymExpr->getSymbol().getName() == "__tls_get_addr" &&
200 "Unexpected function for TLS_CALL");
201 #endif
202 return 0;
203 }
204
205 MCFixupKind Kind = MCFixupKind(SExpr->getFixupKind());
206 Fixups.push_back(MCFixup::create(0, Expr, Kind));
207 return 0;
208 }
209
210 unsigned SparcMCCodeEmitter::
getBranchTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const211 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
212 SmallVectorImpl<MCFixup> &Fixups,
213 const MCSubtargetInfo &STI) const {
214 const MCOperand &MO = MI.getOperand(OpNo);
215 if (MO.isReg() || MO.isImm())
216 return getMachineOpValue(MI, MO, Fixups, STI);
217
218 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
219 (MCFixupKind)Sparc::fixup_sparc_br22));
220 return 0;
221 }
222
223 unsigned SparcMCCodeEmitter::
getBranchPredTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const224 getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
225 SmallVectorImpl<MCFixup> &Fixups,
226 const MCSubtargetInfo &STI) const {
227 const MCOperand &MO = MI.getOperand(OpNo);
228 if (MO.isReg() || MO.isImm())
229 return getMachineOpValue(MI, MO, Fixups, STI);
230
231 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
232 (MCFixupKind)Sparc::fixup_sparc_br19));
233 return 0;
234 }
235
236 unsigned SparcMCCodeEmitter::
getBranchOnRegTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const237 getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
238 SmallVectorImpl<MCFixup> &Fixups,
239 const MCSubtargetInfo &STI) const {
240 const MCOperand &MO = MI.getOperand(OpNo);
241 if (MO.isReg() || MO.isImm())
242 return getMachineOpValue(MI, MO, Fixups, STI);
243
244 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
245 (MCFixupKind)Sparc::fixup_sparc_br16_2));
246 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
247 (MCFixupKind)Sparc::fixup_sparc_br16_14));
248
249 return 0;
250 }
251
252 #define ENABLE_INSTR_PREDICATE_VERIFIER
253 #include "SparcGenMCCodeEmitter.inc"
254
createSparcMCCodeEmitter(const MCInstrInfo & MCII,const MCRegisterInfo & MRI,MCContext & Ctx)255 MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII,
256 const MCRegisterInfo &MRI,
257 MCContext &Ctx) {
258 return new SparcMCCodeEmitter(MCII, Ctx);
259 }
260